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Pre-silicon prototyping is a new technology for many companies, but at Intel, it's important enough to warrant a dedicated support team. At the Electronic Design Process Symposium (EDPS 2014) on April 17, Chris Lawless, director of pre-silicon platform acceleration at Intel, showed how and why his company uses pre-silicon prototypes and made very clear what Intel needs from providers of these platforms.
Pre-silicon prototypes can serve the needs of architects, software developers, hardware designers, and verification teams. The tools include platforms for virtual prototyping, emulation/acceleration, simulation, and FPGA-based prototyping. And through it all, Lawless said, Intel wants a "singular environment" in which diverse users can employ the same models and have the same interface and user experience—a level of integration that Intel has not yet found today.
Even so, pre-silicon prototypes have significantly reduced schedule time at Intel, Lawless noted. These prototyping platforms are facilitating a shift in computing—a move away from long-lead-time, general-purpose solutions like PCs and towards highly time-sensitive, customized solutions like phones, wearables, and other mobile devices. This new electronics marketplace requires planning, architectural and design teams that are very agile, along with prototyping solutions that these teams can use.
What SoC Developers Need
Companies such as Intel that develop systems on chip (SoCs) face a number of tough requirements. First, Lawless said, there's a need to design silicon that goes into a broad range of different computing devices. This brings with it a need to reuse "much if not most of the IP" across different products. Second, customers expect affordability, and skyrocketing design costs must come under control. Finally, customers are demanding more features more frequently, bringing with it a rapid "market refresh rate."
One way to shrink time-to-market and keep costs under control is to perform a "shift left," which means that activities such as software design and hardware/software validation are performed earlier in the product lifecycle. "We have employed shift left, and this helps significantly at Intel," Lawless said. "For example, much of our logic bug hunting was once in the post-silicon phase, and we've moved it to well before tapeout."
However, shift left has its limits. Lawless noted that "you can't shift left before the product is conceived." Shift left works for hardware/software co-validation because that work can be done earlier—but hardware/software co-design is not so simple because it "changes the entire process. It has implications on the architecture and design teams other than schedule."
That's not to say that earlier hardware/software co-verification isn't a big win. "Instead of moving in a siloed fashion, we are actually bringing the hardware and software together and testing it on the use cases and models we're going to deliver to the customer," Lawless said. "It's a novel thing for a big company like Intel." Also, he noted, pre-silicon platforms are turning design and validation into "one continuous activity" at Intel.
More Connection Needed
Still, the pre-silicon prototyping market is in its infancy, and Lawless wants to see some changes. "For the most part, ecosystem suppliers provide disconnected sets of pre-silicon prototyping solutions," he said. "This drives all sorts of extra work throughout the design and validation process."
Some of that work, he said, involves writing and then re-writing test content to be compatible with various pre-silicon platforms. Intel users often develop models for one platform that cannot be reused on another platform, and are unable to share test content between simulation and emulation. Users cannot easily cross-compile models across different platform solutions.
"In this greatly compressed process, I don't have any more time to waste," Lawless said. "I don't have time to build something and rebuild it again on another platform." He noted that Intel uses platforms from multiple vendors and said "there will still be a need for vendors to contemplate the fact that it's going to be a multi-vendor development environment. We want to leverage a seamless continuum of solutions."
Turning his attention to EDA providers, Lawless said that "I would ask that the solutions you deliver contemplate the need for continuum across the product life cycle and seamlessly support reuse from platform to platform. My heaven would be to develop once for a pre-silicon platform, use that content with little change across all the pre-silicon platforms, and my users aren't even aware of what's underneath."
Lawless' talk about pre-silicon prototyping platforms set the stage for a robust session on that topic, as well as a panel discussion on the electronic system-level (ESL) design flow. I'll report further in subsequent blog posts. Cadence was a gold sponsor of EDPS 2014. The presentation for Lawless' talk is available at the EDPS web site.
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Electronic Design Process Symposium (EDPS) Reviews Design Flow Challenges and Solutions
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Chris' EDPS Kickoff keynote was very fitting to the workshop-style Symposium. It was interesting to hear from Intel on this subject. Given the mix of virtual prototype capabilities and goals, plus when combined with legacy IP, makes it a challenge for Intel or any company to implement. After hearing Chris I think he/they can do it.
Good Article. The need for a "singular environment" statement echo's the pain that the emulation teams go through in a product cycle.
Very good and valuable information on pre-silicon prototyping importance and market value for the same.