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One of the busiest spots on the Design Automation Conference (DAC 2014) show floor was the Cadence Theater, which featured continuous customer and partner presentations over a three-day period June 2-4. These informal, half-hour presentations allowed engineers to learn about problems and solutions from other engineers, and to hear about the latest capabilities from Cadence ecosystem partners.
Most of the Cadence Theater presentations are now available in the form of audiotapes and slides at the Cadence DAC web site. Companies who have made their presentations available include AMD, Altera, Bluespec, Broadcom, Cisco, CSR, Dini Group, Fujitsu, GLOBALFOUNDRIES, IBM, Kozio, Maxlinear, Methodics, Methods2Business, National Instruments, NetSpeed, NVIDIA, Samsung, Solarflare, STMicroelectronics, Tektronix, TowerJazz, X-FAB, and Xilinx. Additionally, the Cadence Academic Network held a PhD Forum Award ceremony at the theater.
The Cadence Theater attracted large crowds over a three-day period.
The presentations are available to anyone. To access them, simply go to the Theater section of the Cadence DAC web site and select the sessions you'd like to view. Following is a list of what's available as of this writing. To see a summary of the Cadence Theater 2013 presentations, click here.
Monday, June 2, 2014
Cadence In-Design VIPVS and LDE Adoption in STM Smart Power PDK
Collaboration Key to Enablement at Advanced Nodes
Physically Aware RTL Synthesis
Using Cadence PVS for Signoff at TowerJazz
Post- and Pre-Silicon Verification - The Best of Both Worlds
Foundry DFM Requirements with Cadence In-Design, Signoff DFM
Palladium for Android SW Validation, GPU Testing on ARM v8 SoC
NetSpeed Systems: Bringing the Power of Synthesis to SoC Design
Industry-Leading Solutions for FPGA-Based Prototyping
Application-Level Power Event Monitoring with Hybrid Emulation
SoC Static Power Verification with Encounter Conformal Low Power
Tempus Timing Signoff Solution: Impressions, Real-World Results
Tuesday, June 3, 2014
Analog/MS Flow with EAD, Device Checker, and PVS PERC Features
14nm FinFET Design Using Virtuoso Advanced Features
Overcoming Patterning-Induced Place-and-Route Challenges at 10nm
IP and Design Data Management for SoC Designs
Emulating a Dual-Port 10G/40G NIC on Palladium and RPP
Validate Complex Multi-Core Designs, Optimize HW/SW Performance
Physical RTL Synthesis Improves Timing and Congestion at Fujitsu
Virtuoso Mixed-Signal "SmartPower" Implementation Flow
System Signal Integrity Expands into the Lab
Wednesday, June 4, 2014
SystemC-Based Design for Next Generation of Wi-Fi 802.11n MAC IP
Applying Post-Silicon Verification Approaches at Pre-Silicon
Flip-Chip Co-Design Planning Using Cadence OrbitIO
Accelerated VIP, a Deep Dive Based on Customer Case Studies
Enabling Cadence Signoff Technologies for 14nm FinFET at Samsung
Hardware Solutions for FPGA-Based Prototyping
Old and New DFM Paradigms Transitioning from 20/14 to 10nm
Using Palladium/VSP Hybrid to Accelerate SW Development
Physical RTL Synthesis Strategies on Networking ASICs at Cisco
Enhanced Black Box Design Flow Using Cadence PVS
Cadence Academic Network
DAC - PhD Forum Award Ceremony
FPGA Prototyping Enables Rapid Development of Customizable Processors
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DAC 2014 Cadence Theater - Customers, Partners Outline Challenges and Successes
DAC 2013: Customer and Partner Presentations Now Available from Cadence Theater