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Over the past 14 months Cadence has brought massive parallelism to static timing analysis (Tempus Timing Signoff Solution) and power analysis (Voltus IC Power Integrity Solution). Today (July 14, 2014) Cadence is announcing the Cadence Quantus QRC Extraction Solution, a next-generation parasitic extraction tool that leverages massive parallelism to deliver up to 5X faster turnaround time.
Like its predecessor, Cadence QRC Extraction, Quantus QRC Extraction Solution supports both custom/analog and digital designs. In addition to massive parallelism, the solution provides significant modeling enhancements to support accurate FinFET parasitic extraction, and also includes a new high-performance "random walk" field solver. This week Cadence is announcing that TSMC has certified Quantus QRC Extraction Solution for 16nm FinFET.
According to Hitendra Divecha, senior product marketing manager at Cadence, massive parallelism allows Quantus QRC Extraction Solution users to scale to an "unlimited" number of CPUs and machines to enable the fastest possible design closure. This is particularly important for advanced-node SoC designs, where teams are coping with rapidly increasing design sizes, an explosion in the number of process corners, an increasing number of parasitics, and complex modeling challenges such as double patterning and FinFETs. Accuracy, performance, and capacity are the main three key care-abouts for designers, and Quantus QRC Extraction Solution delivers in each of these areas.
What Came Before Quantus QRC Extraction Solution
To put Quantus QRC Extraction Solution in perspective, it's helpful to review the previous version of the tool, called Cadence QRC Extraction. This tool was a full-chip parasitic extractor that delivered both in-design and signoff extraction. It supported both transistor-level and cell-level extractions, and was closely integrated with both the Cadence Encounter Digital Implementation system and the Cadence Virtuoso custom design platform.
Cadence QRC Extraction offered capabilities such as multi-mode/multi-corner extraction, PowerMOS extraction, inductance extraction for both digital and custom/analog flows, RLCK reduction, substrate noise analysis, statistical extraction, and design for manufacturability (DFM) support. It included an integrated, foundry-qualified field solver.
As the diagram on the left shows, Cadence QRC Extraction didn't only provide a signoff extraction that takes place just prior to tapeout. Using the same engine, it also ran "in design" during the IC digital physical design process, where it helped guide layout decisions as they were being made. This helped design teams avoid rework and reduce iterations.
Iin Cadence QRC Extraction, three extraction modes used the same QRC engine for digital design. One was Turbo QRC, which ran up to 2-3X faster than signoff. Another was Integrated QRC, which was used for ECOs and incremental extraction. It was faster than signoff and it extracted only changed nets. Finally, Signoff QRC was a full-blown, foundry-qualified signoff extractor that includes a 3D field solver. All of these modes supported multi-corner extraction. Likewise, the new Quantus QRC Extraction Solution offers these three modes and provides both in-design and signoff capabilities.
On the custom/analog side, Quantus QRC Extraction Solution is tightly integrated into the Virtuoso custom design platform and can be invoked directly from the Virtuoso user interface. The solution supports in-design extraction with the Virtuoso Analog Design Environment (ADE) as well as signoff extraction.
What Quantus QRC Extraction Solution Adds
Quantus QRC Extraction Solution offers all the functionality of Cadence QRC Extraction, and it supports the same foundry-certified and qualified "qrctechfiles." Quantus QRC Extraction Solution also has some important new capabilities. Foremost is massive parallelism, which allows the solution to provide 5X faster turnaround times for both single and multi-corner extraction runs. Since timing signoff closure can take up to 40% of the IC design flow, a 5X speedup can give a chip design team a tremendous advantage. Further, the incremental extraction capability available with the Encounter platform and the Tempus Timing Signoff Solution can provide an additional 3X performance improvement.
According to Divecha, Quantus QRC Extraction Solution runs 7-8X faster than Cadence QRC Extraction for some design styles. While the earlier product would not provide linear scalability beyond 32 CPUs and above, there is no limit at all for Quantus QRC Extraction Solution, which provides linear scalability for an unlimited number of CPUs. Adding more CPUs for Quantus QRC Extraction Solution yields a close to linear speed increase - for example, going from 16 to 32 CPUs can provide close to 2X the performance, depending on design style.
Accuracy is as important as ever, and Quantus QRC Extraction Solution uses the same high-accuracy modeling engine that is used in QRC Extraction. The result is silicon-proven "best-in-class" accuracy, according to Divecha. In addition, there is less than 1% sigma difference between single-corner and multi-corner extractions.
Quantus QRC Extraction Solution also includes Quantus FS, a random walk 3D field solver that is faster than the previous QRCFS solver.
While FinFETs promise tremendous speed and/or power advantages at process nodes below 20nm, they place some new demands on extraction tools. For example, because of the 3D structure of a FinFET, new parameters such as Cgs (gate to source capacitance) are required. An explosion in parasitics results in a larger netlist, slowing post-simulation layout performance. Custom/analog designers can no longer wait to see the impact of parasitics post-layout -- they need feedback during the schematic simulation phase. Finally, signoff extraction must be deeply integrated with placement and routing to improve post-route optimization and guarantee convergence in signoff.
With FinFETs, extraction tools must be aware of fringe 3D capacitances from gates and fins. The thickness of the gate introduces new capacitances. There are many new sources of resistance as well. Tools need to model three different resistance types -- contact resistance, spreading resistance, and extension resistance.
Quantus QRC Extraction Solution provides accurate modeling of FinFET parasitic effects. Additionally, even though FinFET parasitics typically expand netlists, Quantus QRC Extraction Solution produces a netlist that is 2X smaller than those from competing solutions. As a result, simulation runtimes are 2.5X faster than competing solutions.
The diagram below shows a Cgs design flow in the Virtuoso platform. Instead of waiting until the very end of the design process to run parasitic extraction, engineers can generate a partial layout and run in-design extraction from the Virtuoso ADE front-end tool. In this way, the post-schematic simulation is much more likely to match the post-layout simulation, convergence comes easily, and design iterations can be avoided.
Taken together, Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, and Voltus IC Power Integrity Solution - all Cadence electrical signoff solutions -- are solving tough signoff problems by using massively parallel architectures. As such, they are easing one of the worst bottlenecks in IC design, and they're pointing the way for EDA solutions of the future.
For further information about Quantus QRC Extraction Solution, visit www.cadence.com/news/quantusqrc.
Related Blog Posts
Tempus - Parallelized Computation Provides a Breakthrough in Static Timing Analysis
Voltus - Massive Parallelism Speeds Power Integrity Analysis and Signoff Closure
EDPS Workshop - a Review of FinFET Parasitic Extraction Challenges