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The big news at the CDNLive Silicon Valley Cadence user conference, held March 10-11, 2015, was the Cadence® Innovus™ Implementation System. This massively parallel IC implementation toolset claims 10X faster turnaround times than existing solutions, and it provides a new placement engine, enhanced concurrent optimization capabilities, and a tight integration with power and timing signoff. A keynote speech by Anirudh Devgan (right), senior vice president for the Digital & Signoff Group at Cadence, gave a first look at Innovus just minutes after the news became public.
Devgan portrayed Innovus as a complete IC implementation platform with “dramatic improvements,” including a 10X improvement in runtime and capacity. What’s really important, he said, is “absolute” runtime, which means how much work you can do in a given period of time. “In 24 hours, we can run one-to-two-million instances or more,” he said. “These used to take five days to do.”
More specifically, Devgan showed how a cell design with 9.3M instances got a 9.7X speedup, while a 3M instance cell design got a 7X speedup. He said that Cadence has applied Innovus to chips in a wide variety of markets (mobile, automotive, networking, others) and continues to see “a massive speedup for different classes of design.”
Where does this speedup come from? As shown below, Innovus has a massively parallel architecture, and it supports multi-threading and distributed network processing. Innovus can also handle very large blocks (5-10+M instances), which saves design time because there are fewer blocks to integrate. Advanced-node designs can now have over 100M instances, and if the block size is limited to 1M instances, integrating 100 blocks is very time consuming.
Meanwhile, Innovus comes with a brand new placement engine, GigaPlace. This solver-based engine employs a global optimization strategy. The GigaPlace engine is slack-driven and tightly integrated with timing analysis and optimization. It is electrically driven, physically driven, and optimization driven.
Innovus also uses the Cadence GigaOpt optimization engine. In the past, Devgan noted, GigaOpt focused on timing. In Innovus, it is also power-aware and area-aware, and it optimizes all aspects of power, including leakage, switching, and internal power.
Innovus also provides new technology in clocking. In 2011, Cadence purchased Azuro, a provider of “clock-concurrent optimization.” Now Cadence is offering what Devgan called the “next generation of clocking,” with concurrent clock and datapath optimization. To reduce cross-corner variations, and drive maximum performance with reduced power, designers can use a flexible H-Tree (FlexH) topology.
While speed is really important, Devgan said, what is really critical is power, performance, and area (PPA). He said customers are experiencing 10-20% better PPA with Innovus, “almost like a single process-node transition.”
Devgan noted that Cadence has been working with ARM on the development of Innovus. According to a statement from ARM in the Cadence Innovus press release, “We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM® Cortex®-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target.”
Devgan showed a series of high-performance CPU design benchmarks using Innovus. In one case, with a 28nm chip, there was a 12% power improvement; in another, with a 16nm chip, utilization improved by 18%. In a third case, a 20nm CPU exceeded 2GHz. “I think there is still too much customization for CPUs,” Devgan said. “Some designs take two or three years. Because of better placement [in Innovus] you don’t have to do all that customization.”
Showing an example of a 28nm broadband chip with 3M instances, Devgan noted that current IC implementation tool sets would require that an engineer divide this design into 500K or 1M instance blocks and put it back together. Innovus, in contrast, would allow the designer to work on a flat design. “If you handle the design flat, you can get 10% better area,” he said. “You’re able to optimize all of it together. The other benefit is that the number of required engineers goes down.”
Devgan emphasized that Innovus will support mixed-signal designs through a tight integration with the Cadence Virtuoso platform. This capability uses the OpenAccess database and is already provided with the Encounter Digital Implementation System. “Innovus supports that [integration] fully and improves upon it,” he said.
Integration with signoff is an important Innovus capability, and it will be more important as designers move to lower process nodes, Devgan said. “When they go to signoff, customers still go back and forth and it can take six weeks. That is outrageous!”
Innovus and the Cadence Tempus Timing Signoff Solution use the same code base and database, “meaning that when you are in Tempus you have access to all Innovus place-and-route optimization,” Devgan said. The result is a 5-10X overall speedup in design closure.
Innovus also works closely with the Cadence Voltus IC Power Integrity Solution. Typically power signoff comes at the very end of the design flow and is separate, Devgan said. Innovus makes it possible to run power analysis much earlier in the flow, letting designers free up area for routing.
Devgan noted that Innovus is “ready-to-use production software,” and he pointed to endorsements from Freescale, Juniper, Renesas, Maxlinear, and Spreadtrum. He concluded by saying that “we want to work much more closely with our customers. R&D is open and evolving. If there are issues, we want to make sure you have access to our R&D people.”
A landing page has more information about Innovus.
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