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You might think that an IC digital implementation toolset, such as the Cadence Encounter Digital Implementation System, is only useful after RTL is developed and synthesized. But that's not necessarily the case. At the recent ARM TechCon conference, Cadence and Cisco Systems presented a flow that Cisco is using to do pre-RTL architectural analysis with Encounter.
The paper was titled "Early Architectural Planning for Increased Productivity, Predictability and Profitability," and was presented by Abha Maheshwari, product manager at Cadence, and Krishna Kumar, senior hardware engineer at Cisco. Proceedings are available to conference attendees at the ARM TechCon web site.
In brief, the flow captures design and technology information in a text file, uses a Tcl script to create a netlist, and then uses the automated floorplan synthesis capability in Encounter to generate an early floorplan. Cisco engineers can then obtain early die size and cost estimates, try different architectural alternatives, and develop a preliminary floorplan that can be provided to an ASIC vendor.
"Using our place and route solution and some scripts, we've been able to come up with a complete flow to do architectural analysis very early in the design stage before you even have any RTL ready," Maheshwari said. She summarized the advantages of this approach in the following slide:
Kumar then talked about Cisco's motivations for adopting early architectural analysis. He noted that his group targets different market segments with its networking ASICs, and must meet different requirements. Further, at advanced nodes, wire delays are dominating cell delays. "This means your top level implementation is going to be much more critical," he said. "The best way is to start very early in the design cycle, without coding any RTL, and do an analysis of the design and find out where the bottlenecks are."
Kumar walked through the architectural analysis flow in detail. It starts with the capture of chip architecture and IP information in a text file. Then, a simple Tcl script creates a netlist from this early architectural information. The script adds dummy cells, dummy flops, dummy or real memory, pipeline stage registers, timing constraints, and clock definitions.
An interactive schematic visualization capability in Encounter lets designers view and check the connectivity between different modules. The Encounter GUI can also help designers analyze the implementation feasibility of dummy memory and IP elements. Additionally, Encounter helps Cisco engineers verify pipeline flip-flop insertion, and set up bus guides and net groups.
The next step is automated floorplan synthesis, which was described by Maheshwari. She showed how this capability can take in seed information (or generate its own), optimize the data path, place modules and hard macros, and "provide a very good starting point floorplan in a short amount of time." Designers can generate multiple floorplans and select the best one to meet their goals.
From Two Months to Two Weeks
During his presentation, Kumar noted that prior to using the early architectural flow, Cisco would sometimes wait 2-3 months for an ASIC vendor to come back with die size and cost information. "Right now we are able to do this in two weeks, because everything is done in house without any RTL," he said. Today, he noted, Cisco and Cadence are working together to develop and strengthen capabilities such as automatic bus guide creation, identification and placement of pipeline flops, and what-if analysis for the top-level pipeline. Present and future Encounter Digital Implementation System users will benefit from this work.
Other blog posts about ARM TechCon 2011 papers:
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
ARM TechCon Paper: "Tips and Tricks" for ARM Cortex-A15 Designs
ARM TechCon Paper: Why DRAM Latency is Getting Worse
ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development