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One important enabling technology of a transaction-level modeling (TLM) based design flow is an ability to verify the results of high-level synthesis. Calypto Design Systems, a member of the recently-formed Cadence System Realization Alliance, is playing an important role by closely integrating its SLEC sequential equivalence checker with the Cadence C-to Silicon Compiler.

The following video interview with Tom Sandoval, Calypto CEO, was taken right after a talk given by Sandoval at the Cadence booth at the June Design Automation Conference. In the video clip, Sandoval tells why sequential checking is a must for high-level synthesis, how SLEC works with C-to-Silicon in a fairly automated fashion, and how sequential optimization fits into the EDA360 vision.

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In an additional comment, Sandoval noted that sequential equivalence checking has a role to play in the RTL space as well. If you optimize an RTL design for power or performance, he noted, you'll very likely make sequential changes - such as adding pipeline stages or using sequential clock gating. A sequential checker is needed to verify such changes. Calypto's PowerPro product, in fact, optimizes RTL designs for power and is based on the company's sequential analysis technology.

In his presentation at the Cadence booth, Sandoval noted that "next-generation EDA" will need to move "from combinational analysis to sequential analysis as a technology basis." It's an interesting thought that goes beyond just formal equivalence checking and extends into implementation and optimization, with potential applications from concept through gates.

Richard Goering