Insights into what you can expect at 32/28nm and below came to the forefront at the Common Platform Technology Forum Jan. 18, a well-attended one-day event in Silicon Valley. One point that caught my attention is that IBM is turning to a "gate last" high-k metal gate (HKMG) technology at 20nm.
On the eve of the forum, ARM and IBM announced a design platform collaboration that will extend down to 14nm. Cadence, meanwhile, announced a qualified 32/28nm Silicon Realization reference flow for the Common Platform alliance. This flow extends from RTL synthesis to GDSII signoff for low-power HKMG technology.
The forum featured six keynote speakers. Three were from each of the Common Platform partners -- Samsung, GLOBALFOUNDRIES, and IBM. Three were from ecosystem partners -- ARM, Samsung Electronics (consumer products), and Qualcomm. The forum also included a panel discussion on collaboration, which I'll blog about separately.
What's Driving the Move to Advanced Nodes?
Who needs to design chips at 28nm and below? Speakers noted several driving forces, particularly smartphones, which seem poised to become the next generation compute platform. Here are some "factoids" I picked up from the presentations about smartphones:
Other driving forces include tablet computers, which are replacing PCs, and "smart" TVs. In addition to "smart," everything will be connected. ARM CTO Mike Muller talked about hundreds of millions of networked devices embedded in everything from bodies to buildings. Devices will need to be low-power and very compact, resulting in an acute need for advanced-node semiconductors. Said Chia Song Hwee, COO of GLOBALFOUNDRIES: "We will need more capacity, not less."
Gate-First HKMG Propels 32/28nm
The three Common Platform alliance speakers noted that the 32nm node is production-ready today, with 28nm right behind it (although I don't recall hearing a date). Stephen Woo, president of Samsung's System LSI Division, talked about the advantages of HKMG at 32/28nm. He said this technology results in lower leakage, higher performance, and better manufacturability. He noted that first-pass silicon has been successful and pointed to the ARM Cortex-A9, manufactured in 32nm HKMG, with 1.6GHz frequency and a Vdd of 1.0V.
Different foundries have taken different positions in the "gate first" versus "gate last" approach to HKMG. Compared to 28nm gate-last HKMG, Woo said, 28nm gate-first HKMG offers 10-20% smaller die, a simpler process, faster time to market, and better scaling.
Hwee had more numbers. He said that 28nm HKMG offers a 100% density improvement over a conventional 40nm process, up to 50% increased speed, and up to 50% power improvement. With a smaller die compared to gate-last HKMG, chip companies could save $75 million over 4 years, he calculated. 32nm is ready today "and now we just need to work on the shrink to 28nm," he said.
Going Down to 11nm
Gary Patton, vice president of IBM's Semiconductor Research and Development Center, focused more on what lies below 28nm. He gave a similar talk at last year's ARM Techcon, and I blogged about it here. Then and now, he cited a warning that technologies like HKMG take 10 years of research before they're ready for development. It is thus not too surprising that IBM research today is focusing on nanotechnology - silicon nanowires, carbon nanotubes, and self-assembly techniques.
Patton spoke at some length about lithography. IBM pioneered immersion lithography, he said, and that has improved numerical apertures down to 28nm. But no further improvement is available beyond that, so IBM developed source-mask optimization for the 20nm node. This technology uses a programmable light source and computation that co-optimizes that light source with the mask.
At 14nm, Patton said, there is no way to avoid double exposure (double patterning). Extreme ultraviolet (EUV) may be available by then, but it will have to be cost-competitive. At 11nm foundries will have to have EUV or the result will be "very complex and costly multilayer processing." Further, at 14nm and 11nm, fully-depleted devices will be needed, he said.
Patton epxlained why IBM will use gate-last HKMG at 20nm. While gate-first provides advantages at 28nm, those advantages mostly go away at 20nm, he said. That's because the 20nm node uses a restricted layout structure that is very similar to a gate-last approach. Gate-first HKMG thus offers no density benefit at 20nm, and gate-last power and performance is actually better, thanks to the advent of strained silicon.
A Foundry Customer's Warning
Jim Thompson, senior vice president of engineering at Qualcomm, also talked about advanced nodes, but he sounded a warning. He noted the complexity of advanced nodes and the billion-dollar costs of process development. "We at Qualcomm have a lot of concern," he said. "If we're going to continue to shrink to the next node, and it doesn't become cheaper - if we can't continue to reduce costs as we have for the past 40 years - it's a very significant problem. It's not just about reducing geometries, it's about getting costs down as well."
His parting words: "It's really important for an ecosystem to come together." Cadence agrees.