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If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information. Now in its 7th year, IP Talks! includes over 30 half-hour live presentations and ChipEstimate TV showings running between 10:30 am and 5:00 pm Monday through Wednesday, June 3-5.
"IP Talks! is where you can meet with and hear from the world's leading IP suppliers and foundries as they address the engineering challenges faced by today's chip design teams," said Sean O'Kane, executive director of ChipEstimate.com. These talks, he said, allow DAC attendees to "learn how the latest in semiconductor IP can accelerate their design success."
IP Talks! takes place in an informal setting at the ChipEstimate.com booth
This year's IP Talks! includes IP providers such as Cadence, Synopsys, True Circuits, Open-Silicon, eSilicon, Silicon-IP, and Uniquify. You can learn about Cadence design IP at 1:30 pm Monday and 2:30 pm Tuesday, and hear about Cadence verification IP at 2:30 pm Wednesday. A complete schedule is located here. ChipEstimate.com will be located at booth #2446 in the Austin Convention Center.
Also at the ChipEstimate.com booth, you can see demonstrations of IP exploration and chip estimation, and discover how to estimate your next chip's size, power and cost. One more incentive - if you come to the 11:30 am or 3:30 pm talks any of the three days, you can win a Google Nexus 7 or a Samsung Chromebook. A free cocktail event will be held Monday and Tuesday at 5:00 pm.
Need more convincing? Take a minute (literally) to watch the following video clip, in which Sean O'Kane tells you why these talks are "your DAC resource for all things IP." If video fails to open, click here.
Finally, presentations from previous years are available here (scroll to bottom of the schedule).
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