Get email delivery of the Cadence blog featured here
Are you running design rule checking (DRC) on your PCB layouts? You should—but DRC alone is not sufficient for complex, signal-integrity prone boards, according to a recent presentation by Joy Li (right), solution flow architect at Cadence.
The presentation was titled “Advanced PCB Layout Checks for Power-Aware Signal Integrity,” and it took place before a standing-room-only crowd at the DesignCon 2015 conference on January 28. In the presentation, Li introduced two new levels of layout checks—geometry-based electrical rule checking (ERC) and simulation rule checking (SRC). Combined with DRC, these new checks will provide PCB designers, layout engineers, and signal integrity specialists with advanced layout checking options that provide more insight into a design’s electrical performance.
Li noted that DRC is a good starting point for PCB signal integrity. However, as designs get more complicated, design rules get more complicated too. DRC becomes harder to set up and it tends to be too conservative. DRC uses millimeters or microns, not millivolts and picoseconds.
“There is a huge gap between layout designers and signal integrity engineers,” Li said. “They have different sets of design expertise, they use different tools, and their work is measured in different units. Most of the time they report to different managers and a lot of the time, they are on opposite sides of the Pacific Ocean. What they need is tools that can bridge the gap.”
Li presented an example that shows how ERC finds violations that DRC would not. Suppose we have two trace segments for a given net on the third layer of a six-layer board. Call them trace 9047 and trace 9048. DRC would tell us that both have the same impedance. But trace 9048 actually has four small impedance sections when all layers are considered. This is due to conjoined via anti-pads and plane edges. As Li said, “it’s a look at impedance at a much more detailed level that is reference aware.”
Trace 9047, meanwhile, has one impedance section but is comprised of five coupling sections. This includes two sections of single lines, two sections of two coupled lines, and one section of three coupled lines. ERC would show all that, but automation is needed. This level of information about impedance and coupling would be “almost impossible to find without help,” Li said. “It gets really messy.”
So what exactly is ERC? Li’s definition is as follows:
ERC is a micro, individual, segment-level view in the geometry domain for PCB signal integrity performance. It includes trace reference, trace reference-aware impedance, trace reference-aware coupling, differential pair routing phase, DDR bus group delay and skew, and a number of vias and via locations.
ERC can provide reference-aware impedance and cross-coupling checks, and will ideally display the results in color-coded layouts.
If you’re going to fix a violation, you need to weigh the costs of the violation against the cost of fixing it. This is hard to determine with DRC and ERC alone. At this point, simulation may help, and that’s where SRC comes in. SRC runs in the time domain and reports results in millivolts and picoseconds. If a violation costs two extra millivolts, that’s important information to have.
Li defined SRC as follows:
SRC is a macro, combined, net-level view in the time domain of impacts due to ERC violations measured in millivolts and picoseconds. The simulation setup considers termination impedance, data rate (pulse width, rise/fall time), and amplitude. Results are expressed in Tx (transmit), Rx (receive), NEXT (near end crosstalk), and FEXT (far end crosstalk) waveforms, and signal integrity performance metrics.
There are four levels of SRC checks, as shown below. These include simulations for single lines and single pairs, coupled traces and coupled vias, ideal and non-ideal power delivery network (PDN), and 3D finite-element analysis based models.
In one example, Li discussed the simulation setup and waveform results for a typical low-end server board. She presented another example in which a Level-3 simulation using IBIS models showed signal degradation due to crosstalk issues.
Li concluded that ERC and SRC can “fill the gap” between DRC and signal integrity performance. Designers can screen the board and identify the worst-case conditions for further analysis, investigate the signal integrity impact of design rule violations and tradeoffs, discover how to fix the problems shown in SRC simulation, and compare ERC/SRC results to known-good designs and reference designs. It all adds up to better designs.
DesignCon 2015 Panel: Why System-Level IP Modeling is Difficult
DesignCon 2015: The Biggest Challenges with System-Level Power Modeling