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If engineers suspect they don't have the best EDA tools for the job, they shouldn't be quiet and complacent - they should be assertive and complain. Promoting that kind of environment is one of seven "rules for methodology investment" presented by Jonah Alben, senior vice president for GPU engineering at NVidia, in a keynote speech Jan. 29, 2013 at the DesignCon conference in Santa Clara, California.
Alben started his fast-moving, half-hour speech by noting that EDA is the key to advancing technology. Yes, Moore's Law tells us that technology advances 2X every two years, but that's only part of the story. "If we were using the same tools and methodologies we used 30 years ago to build our chips today, we couldn't use all the transistors the fab guys have cooked up for us," he said.
In spite of the value of EDA, Alben said, companies tend to under-invest in EDA - "and I'll put my own company in that bucket as well." One reason is complacency. With so many challenges and concerns every day, it's hard to convince people that it's really important to invest in next-generation EDA technology. But this kind of thinking is a "dangerous habit," he said.
"You might think engineers complain a lot, but I find they don't complain enough," Alben said. "They have a certain toolset, they get used to its quirks, and they don't speak up when everybody else in the company is speaking up about what they want to see." He noted that "engineers tend to find a way to live in whatever environment they're put into."
Seven Rules for Methodology Investment
Alben's "seven rules," drawn from NVidia experience, are helping the company "find the right level of methodology investment," he said. The rules are as follows:'
Cool New Stuff
Alben then moved on to what he called "cool new stuff," talking specifically about GPU-accelerated EDA as his company's next big EDA investment (NVidia is a major provider of GPUs). He said that NVidia is working with EDA partners to develop ways to accelerate logic simulation, signal integrity, SPICE simulation, and gate-level simulation using GPU-based compute platforms. With SPICE, for example, the company has seen a 6X acceleration in model generation. Logic simulation can run 3X faster with testbench overhead taken into account.
"It's amazing how far the industry has gone, and exciting to think about what the next 15 years are going to bring," Alben concluded. "I'm very excited to see how things turn out."
DesignCon runs Jan. 28-31 in Santa Clara, California. Cadence is exhibiting and presenting three papers. For a description of Cadence activities at DesignCon, click here.
Photo by Joe Hupcey III