Get email delivery of the Cadence blog featured here
What is design efficiency? What drives it – languages, abstraction, IP, or tools? Why aren’t more designers using high-level synthesis? These questions and more took center stage at the DVCon 2015 conference March 2, at a lunch panel organized by the Accellera Systems Initiative.
More to the point, why are we having this discussion at DVCon, the premier conference for IC verification engineers? Because conference organizers have the stated goal of “putting the D for design back into DVCon,” and the tutorials scheduled for March 2 focused mostly on design issues, including design with SystemC and SystemVerilog.
Moderator John Aynsley, CTO of Duolos, said he hated dull panels, and his lively and provocative speaking style guaranteed this wouldn’t be one of them. Panelists were as follows, shown left to right in the photos below (job titles not given):
Aynsley ruled out slide presentations, but he did ask the panelists what they were “passionate” about, and here is what they had to say.
What’s Your Passion?
Goodrich – I’ve spent the last 15 years working on high-level synthesis [HLS]. I want to be able to push information down into HLS to do good designs. I’m also interested in the dividing line between software and hardware.
Bowyer – I have also been working in HLS for 15 years. My passion is abstraction. Too many times we see companies who have moved to HLS and they move their design over to SystemC and still write RTL. And they say, why didn’t this work? The answer is abstraction.
Schaffstein – I’m involved in an initiative to get SystemVerilog into the design flow of the Qualcomm graphics team. I’m passionate about being able to code, from a design standpoint, SystemVerilog without fear. I would love to have some basic building blocks that could be used and shared across the industry.
Sheridan – My passion is about shifting left, about virtual prototyping for software development. Also, for architects, we want to do multi-core performance analysis and power analysis. Perhaps it’s a replacement for spreadsheets.
Sutherland – I have two passions. First, the EDA industry is putting so much focus on the needs of huge chips that they forget a lot of designs are much smaller. Secondly, EDA vendors have placed so much emphasis on verification that they lost focus on design.
Questions and Answers
Q: Why do we care about design efficiency? Isn’t verification the big bottleneck?
Bowyer: Design efficiency isn’t only about design, it’s also about verification. If you could bring in a methodology where what you are simulating runs much faster, wouldn’t that help you with both design and verification? I think that’s the concept behind HLS --- to give you a model that simulates 50X faster than what you do today.
Q: How much more efficient can we get?
Schaffstein: I would feel better about coding at a higher level, but I’m not going to suddenly become twice as efficient. Most of my time is spent in debug, not writing code or running the tools.
Sutherland: Verilog lets you do stupid things. If you want to do something stupid the language has to let you do it, but general coding guidelines should catch most mistakes. SystemVerilog helps a lot with things like enumerated types, but a lot more could be done in the language in terms of semantic rules or new constructs.
Goodrich: Once you get to a higher level of abstraction, you can catch bugs that you were finding at a lower level before. Sooner or later in the design, you’re going to have to go to emulation or something else that gives you a lot of cycles. The more you can do prior to that step, the better. If you can root out 90% of the potential bugs at a behavioral level, you will make better use of your downstream resources.
Q: [To audience] Who here uses HLS? (A few hands go up)
[To panelists] Clearly there are companies who use HLS and use it effectively, but here only a few hands go up. What’s going on?
Bowyer – I think you have to look at the subset represented here. Verification engineers probably aren’t going to run HLS. Maybe 10% of designers use HLS.
Goodrich – I think we’re in the same situation we were in 25 years ago with assembly language and compilers. Almost everything was in assembly language, but once compilers got efficient enough and could produce code as good as or better than assembly language, there was a real advantage in going over.
Sutherland – I started in the 1970s doing only machine code, then I discovered assembly language, then I discovered FORTRAN and, wow, it was incredible how much I could code. But I haven’t had the same effect with hardware design. Every time I try to do something in a high-level language I feel like I write a lot more code to get the job done. No light bulb is going on saying this HLL [high-level language] is solving a problem for me.
Q – So what is the key to design efficiency? Is it about abstraction, IP, or better tools?
Sheridan – Some of it is due to IP reuse at a certain level of abstraction. The use of multicore processors helps reduce the amount of design work that is new for each process.
Bowyer – We have gotten more efficient; look at all the things we can do in verification today. With fast processors and simulation farms we can throw a lot of compute power at it, but we can only go so far.
Q – One thing that’s impacted efficiency in software design is agile methods. Will that help with hardware?
Bowyer – We use agile to design our software. Hardware, maybe – but hardware is so much more complicated, and there is a need for feedback in the end. I think agile will have a tough time with that.
“I would like to see us define a subset of SystemVerilog that can be easily translated to a SystemC equivalent. Then we can synthesize at a high level, and engineers like me can use a language they like [SystemVerilog] as opposed to SystemC.”
“With SystemVerilog, I can do the same loops you guys are doing in SystemC, I just can’t do them as fast.”
“Right now, we do C synthesis to RTL, but we have to write some RTL to connect all the modules generated with HLS. I say, use the right tools for the right problem. If you have a DSP type problem, use HLS. If you have high-level connectivity, use RTL.”
“One thing I love about C++ is that unless I specifically ask for it, I don’t have a time wheel. I hate that in Verilog – it gets me into all sorts of nasty race conditions that I don’t want to care about. C++ is great, but the problem is connecting it to an existing hardware SystemVerilog design.”
Parting Comment from John Aynsley
“We’re not in a one-size-fits-all situation. We’re in a pluralist world where there are multiple choices.”
Related Blog Posts
Accellera Portable Stimulus Group – A Step Forward for System-Level Verification
Accellera DAC 2014 Breakfast – What Engineers Really Think about UVM