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For over 20 years, DVCon (Design and Verification Conference) has been a premier Silicon Valley event for functional IC design and verification. In 2014, for the first time, DVCon is going overseas—for DVCon Europe on Oct. 14-15, as well as DVCon India on Sept. 25-26. Since DVCon India is just a few days away as I write this, I'll focus on DVCon Europe in Munich, Germany.

Sponsored by the Accellera Systems Initiative, DVCon Europe will bring together chip architects, system designers, software developers, and IP integrators. Tutorials and technical sessions will cover the latest information about tools, methodologies, languages, and standards used in IC functional design and verification. An exhibit will feature offerings from top vendors. Cadence is a Global Platinum sponsor and an active participant in the technical program and exhibits.

DVCon Europe opens Tuesday, Oct. 14, with 14 tutorial sessions. The morning session includes user-driven tutorials, while the afternoon tutorials are moderated by EDA tool and service providers. Tutorial topics include:

• SystemC
• Advanced UVM (2 sessions)
• Event-B for cyber-physical design
• Virtual prototyping using SystemC TLM 2.0
• Requirements-driven verification methodology
• Easier UVM
• How to's of metric-driven verification
• Creating tests with a graph-based test specification
• Attack SoC power challenges with virtual prototyping
• Algorithm verification with open source and SystemVerilog
• Revolutionary debug techniques to improve verification productivity
• Architecting your UVM testbench for simulation/acceleration
• Extending digital verification techniques for mixed-signal SoCs

Here's some information on two tutorials sponsored by Cadence:

T8: The How To's of Metric-Driven Verification to Maximize Verification Productivity
14:00 - 15:30 Oct. 14
Presented by John Brennan and Matt Graham, Cadence

How does metric-driven verification (MDV) extend to formal and acceleration engines, and from IP level to subsystem and full SoC-level verification? Cadence has matured and extended the MDV methodology it pioneered in 2004 to address new issues and challenges. The methodology and approach are tool independent and will have significance no matter which vendor's tools you are using.

T12: Revolutionary Debug Techniques to Improve Verification Productivity
16:00 - 17:30 Oct. 14
Presented by Nadav Chazan, Cadence

This tutorial will address the integration of post-process and interactive debug capabilities in a multi-language debug solution that can help you fix bugs in minutes as opposed to hours or days. Engineers need only run simulation once after a bug is detected.

Tuesday concludes with a networking reception and Accellera dinner. The conference resumes Wednesday, Oct. 15 with a 9:00am – 9:50am keynote speech by Bernd Adler, wireless CTO and division vice president at Intel Mobile Communications.

Technical paper topics for Wednesday include analog/mixed-signal design and verification, advanced verification, IP reuse, system-level design and verification, low-power methodologies, and verification management. A poster session is available during lunch. The following papers include Cadence presenters and/or authors:

• T4.2 Simulation and Debug of Mixed-Signal Virtual Platforms Enabling Hardware-Software Co-Development. 14:00-15:30
• T5.3 Reboot your Reset Methodology: Resetting Anytime with the UVM Reset Package. 14:00-15:30
• T7.1 Connecting Enterprise Applications to Metric-Driven Verification. 16:00-17:00

Finally, exhibitors will show the latest advancements in functional design and verification tools. See the DVCon Europe website for a list of exhibitors and exhibit hours. You'll find Cadence in booth #3.

For further information and registration, see the DVCon Europe 2014 website, or learn more about Cadence involvement.

Note: The FDL 2014 Forum on Specification and Design Languages will be co-located with DVCon Europe 2014. See the FDL 2014 website for more information.

Richard Goering

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