Get email delivery of the Cadence blog featured here
The DVCon conference, held Feb. 28-March 3 in San Jose, Calif., was by all appearances a success this year. Major events were well attended and the program had a lot of interesting content. While the Universal Verification Methodology (UVM) was a major focus, this year's program made it clear that DVCon is not only about RTL digital verification. Analog/mixed-signal verification was an important topic, as was SystemC and electronic system level (ESL) design.
Here's a summary of blog coverage of major events at DVCon, as well as blog posts that give a general overview. Most of the posts listed here are from the Cadence Community, although several external blog posts are included.
Monday, Feb. 28 - North American SystemC Users Group meeting
Jim Hogan Keynote: Making Money from SoC Realization, Richard Goering
Video: SystemC Update from OSCI Chair Eric Lish, Richard Goering
NASCUG at DVCon 2011, Peggy Aycinena, EDN
Monday, Feb. 28 - Accellera and OSCI UVM "Town Hall Lunch"
UVM Meets SystemC and VHDL in DVCon "Town Hall" Forum, Richard Goering
Accellera and OSCI Joined to Introduce UVM, Gabe Moretti, Gabe on EDA
Tuesday, March 1 - Panel: UVM - Final Answer or Phone a Friend?
DVCon Panelists: What Should Accellera Do Next With UVM? Richard Goering
Tuesday, March 1 - Paper: Mixed-Signal Approaches in Assertion-Based Verification
DVCon Paper: Assertion-Based Verification for Mixed-Signal Designs, Richard Goering
Tuesday, March 1 - Wally Rhines Keynote: From Volume to Velocity
Want 40% better SoC performance with 30% less power consumption? Mentor's Wally Rhines says look to System Realization (without using those words) in his DVcon 2011 keynote, Steve Leibson, EDA360 Insider
Wednesday, March 2 - Panel: Making Great Products Great
Making Great Products Great, Peggy Aycinena, EDN
Wednesday, March 2 - Paper: Optimizing Area and Power Using Formal Methods
Video: Optimizing Area and Power Using Formal Methods, Joseph Hupcey III
Thursday, March 3 - Cadence sponsored lunch: Mixed-Signal is No Longer "The Other Guy's" Problem
DVCon: Mixed-Signal Designers Cite Verification Challenges and Needs, Richard Goering
General Conference Coverage
Video: New Cadence Verification IP Catalog (With Denali Inside), Joseph Hupcey III
TLM 2.0, UVM 1.0 and Functional Verification, Sharon Rosenberg
DVCon? Are You Sure It's Not UVMCon or MSVCon? Tom Anderson
DVCon: Truth and Consequences, Peggy Aycinena, EDN
Free Panel, and Photos From DVCon Day 2, J.L Gray, Cool Verification
Photo by Joe Hupcey III