Get email delivery of the Cadence blog featured here
The ARM Cortex-M0 processor core is increasingly finding its way into analog/mixed-signal applications in such areas as automotive, RF, medical, power management, and display drivers. For many applications, a flexible and scalable architecture with an embedded processor is a far better solution than building custom logic to provide digital control. But using embedded processors in mixed-signal designs poses some challenges, and it requires a comprehensive solution.
To help mixed-signal designers who are using or contemplating the use of the Cortex-M0, ARM and Cadence are co-presenting a Sponsored Session at ARM TechCon Tuesday, Oct. 25 (see my previous blog post for a general overview of the conference). To get some background on the challenges and requirements of mixed-signal design with an embedded processor, I spoke to Mladen Nizic, engineering director at Cadence and a presenter at the session. Following are some perspectives that emerged from our discussion.
What does the ARM Cortex-M0 provide?
The Cortex-M0 is the smallest, lowest power, and most energy-efficient ARM processor available. Its small area, compact code, and low power and 32-bit performance make it very attractive for many mixed-signal applications. The core has just 12K gates (in its base configuration), uses set of just 56 instructions and consumes as little as 3 µW/MHz (0.003 mW). Further information is available at the ARM web site.
Why are designers using the Cortex-M0 in mixed-signal devices?
Analog/mixed-signal devices increasingly require digital control. Digital logic may be needed to control inputs and outputs, drive controllers, run display drivers, process and filter signals, and perform many other tasks. At advanced process nodes, digital control is also increasingly needed for self-calibrating analog circuits.
Traditionally, mixed-signal designers start implementing digital functionality with custom logic, and then quickly find it inefficient due to the increasing amount of digital logic they need to design and integrate. A mixed-signal flow with an integrated capability for synthesis and place and route helps create and implement digital controls more efficiently. Furthermore, using an architecture with an embedded processor such as the M0 brings greater flexibility, since it's a lot easier to modify or write new code than to build new logic whenever functionality changes are required.
What challenges arise when mixed-signal designers adopt an embedded processor?
Designers have to put analog and digital circuits on the same chip and verify that they work together properly. Implementing the core itself is straightforward, and the design methodology predominantly depends on what needs to be integrated with it. The first challenge is functionally verifying the design. IP blocks need to be verified separately and in combination with each other. To achieve this in a reasonable period of time, engineers need to go beyond traditional SPICE simulation and employ faster simulation and verification methodologies.
To minimize power consumption, low power designs techniques are often used in mixed-signal designs. This requires low power verification, implementation, and analysis capabilities in the design flow, and that becomes more challenging in a mixed-signal environment.
Minimizing area is another key challenge that requires the tight integration of analog and digital functionality and efficient chip floorplanning. The correct placement of IP blocks is crucial in order to avoid signal interference, protect sensitive analog circuitry, optimize area, and save power.
Chip integration and signoff with silicon predictability is another challenge. Often a combination of parasitic mixed-signal simulation and static timing analysis is required to confidently sign off on the design.
What kind of flow is needed to overcome these challenges?
A unified mixed-signal flow that encompasses both analog and digital design for verification and implementation is needed. On the verification side, an integrated simulation engine capable of handling different levels of abstraction is required, supported by behavioral modeling techniques.
On the implementation side, a mixed-signal flow that uses a common database for design data and constraints enables optimal floorplanning and chip integration, with visibility into mixed-signal IP blocks for accurate signoff. The Cadence mixed-signal solution offers a highly integrated flow comprising of the production-proven Virtuoso, Incisive and Encounter platforms, and is well suited for these kinds of designs.
What can attendees expect at the ARM TechCon Sponsored Session?
ARM and Cadence will jointly present an overview and discuss the advantages of the Cortex-M0, describe verification and implementation flows for designing mixed-signal applications with the core, and outline available physical libraries and IP.
This is an ideal session for anyone planning on using Cortex-M family, or already designing with it and looking to enhance their mixed-signal methodology, or just wanting to learn something new.
Some further information about the Sponsored Session
The one-hour session will be held Tuesday, Oct. 25, at 2:00 pm in room C at the Santa Clara Convention Center. In addition to Mladen Nizic, presenters include Dominic Pajak, Embedded Segment Manager at ARM, and Raviraj Mahatme, platform marketing manager at ARM. Further information about this session and other Cadence activities at ARM TechCon is available here.