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Will you use FinFET or FD-SOI (fully depleted silicon-on-insulator) technology in your next IC design? At a panel discussion at the recent Electronic Design Process Symposium (EDPS 2015), industry experts debated the advantages and tradeoffs of these technologies for Internet of Things (IoT) and other applications.
A three-hour “FD-SOI vs. FinFET” session started with a keynote speech by Tom Dillinger, CAD technology manager at Oracle (see part 1 of this blog series). It then moved onto a panel discussion, which is described below. The panel was moderated by Dillinger. Participants were as follows, as shown left to right in the photo below:
The entire panel was a Q&A session. Here are some of the highlights.
Q: Jamie, since you [GLOBALFOUNDRIES] support FinFETs and FD-SOI, how would you guide me to one or the other?
Schaeffer: FinFET and FD-SOI can definitely co-exist, and there is an inflection point as people migrate from 28nm to the next node. For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.
Q: Is there a large-volume foundry that is committed to FD-SOI?
Low: We consider ourselves [Samsung] to be a pretty large foundry and we have invested in additional capacity. We have run a lot of 28nm capacity. To attract the next wave of customers, who want either high performance or ultra-low power, FD-SOI is very interesting from a value proposition.
However, SOI is considered rather niche. There is an opportunity to turn it from niche into mainstream, but we can’t do it alone. We need customers who have announced adoption of SOI and we need a lot of healthy activity on the ecosystem side.
Schaeffer: Next-generation FD-SOI performance can approach FinFET performance. Next-generation FD-SOI products have 40% higher performance than the first generation of FD-SOI. They are 30% faster than existing 20nm high-k metal gate products. And they have a very cost-effective process, with 10% fewer mask layers than 28nm bulk technology, or 50% fewer immersion lithography layers than FinFETs.
Q: FD-SOI allows very low supply voltages. How low is the voltage you can really substantiate with accurate modeling? How can you manage variability at 0.5V or 0.6V or whatever?
Dillinger: Boris, perhaps you can take this one. Variability will hit analog design first and hardest.
Murmann: I would say no. Variability is no problem for analog. A digital chip is a sea of transistors that are all minimum size, and all have to work. For analog, maybe there are 100 transistors I really care about. I can upsize them and nobody cares. There is usually no benefit in analog design to lowering the power supply. You can go with 0.7V or 0.8V, but going to 0.5V is really just torturing yourself.
Low: Variability is limited by the headroom you have. You can go pretty low, down to 0.5V these days. Fully depleted architectures have the benefit of not having a variability contribution from random dopant fluctuation. For logic, you can go down to 0.4V so long as the models are accurate.
EDPS is held annually at a resort located on Monterey Bay, California.
Q: For a foundry customer, what would be the plusses or minuses of going from bulk to FD-SOI at 28nm?
Brambilla: I can tell you why we chose FD-SOI versus other technologies. The point is mostly about leakage control. For IoT devices you almost don’t care about power, you care about being done as quickly as possible. You have this burst of activity where you want technology that can run fast enough and get the heck out of the way and shut everything down. What really matters is leakage when you’re supposed to be sleeping.
Q: A lot of companies are moving towards FinFETs, but going from planar to FinFET is a big expense. IoT is a very cost-sensitive market. Is it possible to take FD-SOI devices down to 20nm without changing tools?
Schaefer: I think there are ways to do smart scaling a little before 20nm. But as you hit 20nm there is a real inflection point. You go to double patterning and a more complex middle end-of-line.
Q: I’d like to pull the discussion away from the SOI transistor and talk about interconnect. A lot of dynamic power is in the interconnect. The input capacitance of SOI transistors is significantly smaller than bulk transistors. The current that runs through the interconnect wire would be lower, so power dissipation could be saved. Could anyone comment?
Murmann: Capacitance is the same in FD-SOI as bulk. The only difference from a capacitance perspective is that the junctions drop out, and that gives a little lower current.
What we have found comparing 28nm FD-SOI to 14nm FinFET is that the speed is almost the same. In the FinFET you have smaller intrinsic capacitance, but the extrinsic capacitance is a mess.
For the analog guys this will be a nightmare. The problem we have is the following. In a FinFET process the current you get per width is much higher than the bulk or FD-SOI process because you’ve wrapped the gate around. So now you have less contact to take that current. If you bias a device with pretty high constant current, your contacts electromigrate [EM] away. In some circuits we are completely limited by EM. It’s a beautiful transistor [FinFET] but I can’t use it.
Q: We are making designs more complex, but what about yield and reliability? Talk to us about end of life.
Brambilla: An IoT device probably has a lifetime of 5 years. I will sign off using two-year libraries. I’m leaving some power optimization on the table. But we have products that are qualified and in production now.
Low: Coming into a FinFET, you have limitations because of the higher current capability of the transistor. We introduce EM-related design rules and additional models, and capture some of this in the IP and cell libraries.
Q: What concerns do you have about design for test? Any new tools, fault mechanisms, or testability issues?
Murmann: One thing I want to bring up is layout. After the first layout we did at 14nm, which has double patterning, the student said he would reconsider his career options and that business school may be the way to go. Custom analog layout in technologies that use double patterning is a royal pain. Companies almost have to double the number of layout people, and that’s a huge cost factor.
Low: We provide color-less implementation. As long as they follow the design rules, the foundry can do the decomposition.
Q: Where will things be at EDPS 2020, five years from now, assuming IoT takes off?
Brambilla: I don’t think we’ll need to be at 5nm in 2020. We will, however, need whatever it is that will bring us another 200-300mV down.
Low: Definitely transistors will continue to scale – that will not change. The pace of the scaling will be interesting to see. It all depends on new killer apps, but we haven’t seen the next wave yet.
Murmann: Getting a performance boost from further scaling is going to be limited. It all boils down to cost. We will talk much more about cost in five years than about Ion and Ioff. Also, we will talk much more about interconnect. 2.5D and 3D ICs are coming and more performance gains will come from these systems.
Schaeffer: We will see increased levels of system integration to minimize cost and system power. Advanced packaging techniques will include 3D interposer. We will also see the capability to integrate embedded non-volatile memory into these applications.
Related Blog Posts
EDPS 2015: Choosing FinFET, FD-SOI, or Bulk Planar FETs (Part 1)
EDPS 2015: Have We Hit the Power Floor?
Webinar Review: How FinFET Processes Will Change Analog IC Design