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In the past few years, it has become clear that no single development platform will fulfill all the needs of system-on-chip (SoC) designers and programmers who must do their work before silicon is completed. Today the picture is getting even more complex with “hybrid” platforms that combine the capabilities of existing development platforms, such as virtual prototyping and emulation.
At the Electronic Design Process Symposium (EDPS 2015) held in Monterey, California, in late April, four experts – two from the user community, two from EDA providers – gave presentations on hybrid development platforms and participated in a Q&A session. Participants were as follows, as shown left to right in the photo below:
Prior to this discussion, I thought the term “hybrid” applied to a combination of emulation and virtual prototyping. The idea is that processor models run on a workstation, far faster than they would run in the emulator, while other system hardware runs at the register-transfer level (RTL) in the emulator. But it turns out that there are other types of hybrids. Design teams face a tough challenge when it comes to finding people with the right skill sets to drive hybrids.
Here are some highlights from presentations given by the participants.
Russell Klein – Basics of Hybrid Emulation
Klein pointed out that delivering an SoC is not just about delivering silicon – it also requires drivers, middleware, protocol stacks, and software development kits. He showed a chart that depicts a 17X increase in the software development effort from the 90nm process node to the 14nm node.
Klein listed pros and cons of the major types of development platforms, as follows:
With hybrid emulation, Klein said, we move the processors out of the emulator and place them in a “virtual machine” running on a workstation. The virtual machine also includes memory models and a timer block. Because the virtual machine runs much faster than the emulator, the time to boot an OS (in one example) can drop from 82 minutes in the emulator to 2.2 minutes using the hybrid.
Vikramjeet Singh – Hybrid Makes Waves at NVidia
When NVidia started building SoCs, Singh recalled, the software team could not meet its schedule. This is because they could not start validation until all of the RTL code for the hardware was complete. Then NVidia worked with Cadence to develop a hybrid emulation flow using Cadence Palladium emulators. Now NVidia is meeting its goal of completing software development and validation at tapeout.
With the new flow, Singh said, NVidia teams develop an architectural specification, write SystemC models, and create a full-chip simulator. IP blocks that were developed in RTL are brought into the emulator (or FPGA prototype), and then connected to the SystemC simulator. As a result, hardware/software co-validation can be finished on time.
One initial problem was the lack of a team that put everything together for pre-silicon software development. There is such a team today. NVidia also had some problems synchronizing memory between the CPUs and the IP blocks under test. Cadence helped NVidia develop a memory synchronization technique, and now NVidia has a development environment that makes it possible to boot an OS and run production use cases.
“We love hybrid. I think we’re getting addicted to it,” Singh said. What he’d like to see now is an ability to tune performance pre-silicon.
Vinoo Srinivasan – Several Kinds of Hybrids
Intel’s experience with hybrid platforms came from a need to “shift left” in order to improve time to market. “We wanted our software developers to start doing co-design, start developing the software, and start the integration tests and power management pre silicon,” he said. “This way, you get better quality and get to market faster.”
Srinivasan listed the tools that are helping Intel “shift left,” including several kinds of hybrids:
The last item refers to re-using the previous generation of silicon along with an FPGA prototype.
Srinivasan cited a number of benefits for a hybrid FPGA/virtual platform approach. These include high speed with RTL accuracy, reuse of RTL models, mitigating the lack of a 3rd party virtual platform model, enabling pre-silicon systems with at-speed real-world devices, and “true” pre-silicon hardware/software co-validation. However, what you put in the FPGA and what goes into the virtual platform is an important distinction – it’s complicated to go back and forth between the two.
Frank Schirrmeister – Stop Abstracting!
Schirrmeister has been part of the electronic system level (ESL) movement for many years, and as a “recovering ESL-holic,” he recalled the time when people thought everything would go up in abstraction. “I am convinced that ESL is no longer about trying to abstract everything upwards,” he said. “Instead there is this notion of continuum.” What is important, therefore, is a continuum of connected hardware/software development engines, including virtual platforms, simulation, emulation, and FPGA prototyping.
While noting that there will be many types of hybrids, Schirrmeister focused on “TLM-emulation” [transaction-level modeling] hybrids for early OS and software bring-up. These include the Cadence Palladium/Virtual System Platform hybrid solution depicted below. Virtual models, CPUs, and “smart memory” reside on the virtual platform side. Other system components run in the emulator. Users need to decouple the two domains so the virtual platform side can run at high speeds.
With the hybrid model, users can boot Linux 60X faster than with emulation alone. “If I can get to my point of interest faster, that helps a lot for my overall cycle,” Schirrmeister said.
“The one tool flow for all ideas is really dead,” he concluded. “It requires too much modeling and there is no engine that can do all of it.”
Takeaways from the Q&A Session
Related Blog Post
EDPS 2014: Creative Ways to Use Pre-Silicon Prototyping Platforms