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If you want to understand how chips and systems are designed today, and what challenges lay just around the corner, there's no better place than the Electronic Design Process Symposium (EDPS) in Monterey, California on April 17-18, 2014. Now in its 21st year, this IEEE-sponsored workshop continues to bring together the thinkers, movers, and shakers of the EDA and semiconductor IP industries to review design processes and CAD methodologies.
The EDPS 2014 general chair is Aparna Dey (right), technical marketing director for standards at Cadence. Corporate sponsors include Cliosoft, eSilicon, IPextreme, Cadence, and Arteris. Prominent themes this year include design flow challenges, pre-silicon software development, FinFETs, fully-depleted SOI (FDSOI), 3D ICs, and IP. For the first time, EDPS is offering an "IP Day" on Friday April 18 with a focus on IP- and SoC-related topics.
Fair warning—the beautiful setting may be distracting. The symposium takes place at the Monterey Beach Resort, which is right on the beach, and the sound of crashing surf is always audible. But the presentations will capture your interest, and the workshop is small and informal enough (typically around 50 participants) to allow a high degree of interaction. I have previously called the workshop the "TED Talks of EDA."
EDPS 2013 session at the Monterey Beach Hotel
Keynote speakers at EDPS 2014 include the following:
The workshop includes these sessions:
Further program and registration information is available at the EDPS website. Rates go up March 31, so don't delay.
Cadence Blog Coverage from EDPS 2013
EDPS Workshop—a Review of FinFET Parasitic Extraction Challenges
Electronic System Level (ESL) Design Gets a Pragmatic Look at EDPS Workshop
Panel: 3D-IC Design Experts Tackle "Practical Issues" in 2.5D and 3D TSV Deployment