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In the past few years, high-level synthesis (HLS) from SystemC has become a mainstream EDA product with high quality of results. But there are still a few issues to be resolved, one of which is the identification of structures in SystemC code that can result in routing congestion.
The problem of post-HLS routing congestion—and a congestion detection utility that Cadence recently developed—was the subject of a presentation by Phil Bishop (right), who heads North American and Central sales at Cadence, at the Front-End Design Summit in December 2014. Until this year, Bishop was vice president of the System Verification Group at Cadence.
In a brief introduction to HLS, Bishop noted that HLS takes a high-level SystemC description, does some elaboration and scheduling, and produces optimized RTL code. A big part of the value proposition is architectural exploration. He also noted that by using SystemC, designers are writing less code than they would with RTL-only synthesis, and will have less of a debugging task. Further, HLS today handles both control and datapath logic, and can beat hand-coded RTL when it comes to quality.
Cadence believes in high-level synthesis and wants to have a strong presence in this market. Cadence developed the C-to-Silicon Compiler in the early 2000s, and in early 2014 Cadence purchased Forte Design Solutions, which provided the Cynthesizer tool for SystemC synthesis. In the future, Bishop said, Cadence will offer an integrated HLS solution that “combines the best” from both Cadence and Forte technology.
Any new technology comes with a learning curve—and HLS is no exception. “As we built a lot of production designs, we found that sometimes the automatically generated RTL left a little to be desired in terms of the actual routing of the design,” Bishop said. “We found there was often a tremendous amount of congestion.”
This congestion, Bishop noted, increases design cost, chip size, and design time. “Congestion is at the heart of design closure challenges,” he said.
Routing congestion occurs at both global and local levels. Global congestion refers to connectivity at the chip or inter-module level. Local congestion occurs within a module. Focusing on local congestion, Cadence found that most congestion was caused by SystemC optimizations that led to “bad logic design’’—specifically, designs that had a huge number of muxes and de-muxes. These problems are typically found late in the design cycle.
It turns out that routing congestion is highly dependent on the SystemC coding style. Micro-architectural decisions, such as the use of certain pipeline structures, can lead to congestion. Resource and register sharing during area minimization can increase routing congestion. However, Bishop said, “95% of the congestion we saw was related to SystemC constructs that led to a great deal of muxing and de-muxing.” For example, breaking a loop to perform an RTL optimization can result in a tremendous number of muxes and de-muxes operating in that loop.
Working with engineers from Fujitsu, Cadence developed a wire congestion detection package that identifies the location of SystemC structures that are causing routing congestion issues. It uses the design flow shown below. After finding the structures that cause congestion, the utility reports back to the user with improvement suggestions. The utility can be executed easily and is not tied to any specific tool. It is currently available with C-to-Silicon Compiler.
In one case study, a customer started out with a block that had 8,620 muxes and routing congestion of 8.55% horizontal and 4.28% vertical. After a quick improvement, designers produced a block with 5,158 muxes and routing congestion of 1.79% horizontal and 2.95% vertical. Another round of improvements took a lot more effort, but reduced the mux count to 4,982 and the congestion to 0.17% horizontal and 0.81% vertical. This last example, however, came with a slight increase in area.
Bishop said that future directions for congestion control include more automated detection, reporting, and visualization within the HLS tool itself. Cadence is also looking at scheduling and resource sharing optimizations within the HLS tool that can minimize congestion.
- Front-End EDA Panel: “Empowering” the RTL Designer
- Archived Webinar: An Introduction to High-Level Synthesis (HLS)
- How Cadence Acquisition of Forte Boosts High-Level Synthesis