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With a theme of "where the chip meets the board," DesignCon is the premier technical conference dedicated to signal integrity at the chip, board, and system levels. Produced by UBM Tech, DesignCon 2014 will be held January 28-31 in Santa Clara, California, and Cadence will have a strong presence at this year's event.
First, however, I'll give a quick general overview of DesignCon 2014, which consists of a technical conference and an exhibition (Expo). The Expo runs 12:45pm - 6:00pm on Wednesday, January 29 and 12:30pm - 6:00pm on Thursday, January 30. It features high-speed design tools and solutions for modeling and simulation, test and measurement, prototyping, analyzing, packaging, and more. Over 150 vendors will exhibit, and you will find the vendor list here. A free Expo pass will also get you into the keynote speeches and panels.
Highlights of the 2014 Expo include:
Keynote speakers include Dr. Hermann Eul, Vice President and General Manager, Mobile & Communications Group, Intel (Tuesday): Eileen Bartholomew, Senior Vice President, XPRIZE (Wednesday); and Thomas Pawlowski, CTO and Fellow, Micron Technology (Thursday). At this writing, only a description of the Pawlowski speech is available. He will speak about three revolutions in memory architectures.
The DesignCon 2014 conference includes over 100 sessions across 14 tracks. One new track this year is Wireless and Photonic Design and Integration. Other tracks are as follows:
For a complete overview of the conference program, see the Schedule Builder here.
Last year at DesignCon, Cadence showcased the first integration of the Sigrity signal integrity and power integrity tools with Cadence Allegro PCB design tools (see photo below).
At DesignCon 2014, Cadence will hold ongoing demos of its Allegro Sigrity Integration (ASI) tools at booth #507. Visitors will be the first to see new features in ASI 16.63, including analysis and compliance checking for DDR4 interfaces. Demos in the Cadence booth will include constraint-driven power integrity design and analysis, power-aware memory interface design and analysis, multi-gigabit serial link design and analysis, and chip-package-board co-analysis.
Cadence experts will participate in the following technical sessions:
For further information and registration, see the DesignCon 2014 website. Advance rates expire January 17. For more information on Cadence activities, click here. See you at the conference!
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