Get email delivery of the Cadence blog featured here
It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to Jongwook Kye, fellow for lithography modeling and architecture at GLOBALFOUNDRIES. At the recent CDNLive Silicon Valley 2013 conference, Kye made the case for a new level of collaboration called Design Technology Co-Optimization (DTCO).
Kye's presentation was titled Technology and Design Co-Optimization for 10nm and Beyond. The presentation had 9 co-authors, including Jason Sweis of Cadence. Presentation slides are available at the CDNLive Silicon Valley proceedings site (after logging in, look for session AVD201 under Advanced Node/3D-IC).
Kye began his presentation by noting that process technology development and design are separate "islands," and that technology developers "ship" information to designers using process design kits (PDKs). But this one-way delivery is no longer good enough. "We have to work together with design-aware technology and technology-aware design," Kye said. "What I propose is not a delivery [of PDKs], it is DTCO."
Getting Moore's Law Back on Track
Kye noted that the cost per transistor predicted by Moore's Law held mostly true over numerous process generations, but went off track with 20nm. That's because of the added cost of double patterning. The gap is expected to widen a bit more with 14nm FinFET technology. We can bring the cost curve back on track at 10nm, but only with DTCO, Kye said. "If we just ship PDKs from island to island, we will not be able to get there."
So how can process technology development and design work together? As shown in the diagram below, a starting point is lithography process selection. From this selection, it's possible to identify such characteristics as baseline pitches, critical dimension uniformity (CDU), and overlay. Resolution enhancement technology (RET) must be factored into technology development early. A library, physical layouts, and lithography simulation are then required. The outcome is a set of comprehensive design rules.
Design Technology Co-optimization involves many steps. (GLOBALFOUNDRIES presentation, CDN Live Silicon Valley 2013)
Library development is one of the most challenging aspects of this process, and physical library architecture is a key starting point, Kye noted. Ultra-regular layouts can be very beneficial, but there are a lot of options and tradeoffs to consider. One possibility is making the top metal layer uni-directional, which requires vertical local interconnect and results in fewer fins. As Kye noted, "you have to sacrifice something" to get a cost reduction.
FinFETs "require a lot of attention," Kye said. First, they need gridded rules, resulting in a physical rule challenge for dense libraries. A second requirement is 3D aware layout-versus-schematic (LVS) and parasitic extraction.
Double Patterning and More
Much of Kye's talk was devoted to multiple patterning, which he identified as the "only practical solution" for back end of line (BEOL) semiconductor processes at 20nm and below. There are several approaches to double patterning. Litho-etch, litho-etch (LELE) is the primary technology used at 20nm, but it has some challenges. These include overlay, via alignment, and contact hole pattern CDU.
Even if a library cell follows all the double patterning rules and is DRC clean, there could be a colorization problem when two cells are placed together. Should you flip a cell or create more space between cells? This is "another complicated decision" that requires DTCO, Kye said - "we need to deliver a consensus from working together."
Kye talked about a lower-cost alternative to LELE called litho-freeze litho-etch (LFLE). It reduces cost because it eliminates one etch cycle. However, it's hard to make a trench using this technology. "Once you freeze it, there is no way to punch through it. That's why you don't hear about LFLE," he said.
Can we avoid triple patterning at 10nm and below? Kye's answer was "no," especially for library cells. But we can be creative with smart designs and minimize our use of triple patterning, Kye said. "Let's work together - there's no way to do it with separate islands."
Finally, Kye talked about self-aligned double patterning (SADP), a somewhat complicated process involving sidewall deposition and removal of features with a "block mask." SADP allows more aggressive pitch scaling and avoids the overlay problems of LELE. Compared to LELE, SADP has less impact on net capacitance variation and less impact on RC delay variation.
Kye showed an example of a layout that could not be decomposed in LELE because it would cause a colorization conflict - but it could be decomposed in SADP. However, the router "needs to treat SADP differently from LELE," Kye said. For example, the router needs to consider the pin accessibility difference between LELE and SADP.
Kye's conclusion: "Let's not hesitate to work together. There's no boundary. If we work together we can get better results. The future is waiting for us."
To access slides from this and other CDNLive Silicon Valley 2013 presentations, click here. A Cadence.com log-in is required. The proceedings page gives you the option to create a Cadence.com user account if you don't already have one.