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Design for manufacturability (DFM) requirements have been a barrier for many design teams who are thinking about moving to lower process nodes. But can DFM actually get easier as process nodes shrink? That possibility is offered by DRC Plus (DRC+), a new technology developed by GLOBALFOUNDRIES in collaboration with Cadence.
While DRC+ was announced in June, it's been the subject of some recent attention. Two Cadence Silicon Realization webinars last week discussed DRC+ for custom flows (Oct. 20) and digital flows (Oct. 21), and a paper at CDNLive! Silicon Valley Oct. 26 also describes it. To get the inside story, I talked to Vito Dai, process engineer for DFM at GLOBALFOUNDRIES, and Ya-Chieh Lai, engineering director for DFM enablement at Cadence.
DRC+ is a pattern-based DFM methodology that can be run "in design" by chip design teams well before tapeout. It works much like standard design rule checking (DRC), but instead of just coding rules, it uses shape-based pattern matching to identify layout configurations that could be difficult to manufacture. DRC+ rules are comprised of a yield detracting pattern to avoid and a recommended DFM rule to follow. Designers fix violations by avoiding the pattern or enforcing the rule.
Here are answers to some of the questions I had about DRC+:
What kinds of problems does DRC+ find?
DRC+ finds lithography hot spots. These can also be found with lithography simulation, but that's much more computationally intensive. Example problem: a contact and poly landing pad are positioned too close to a diffusion region.
Does DRC+ replace model-based DFM?
"We don't view it as a replacement for model-based DFM, because there are places where that is still appropriate," Vito said. "It does reduce the need for lithography simulation, but we still use that on our side." Ya-Chieh noted that DRC+ replaces the need to run simulation in many design flows where simulation is too slow.
Does GLOBALFOUNDRIES require DRC+?
It will be a requirement for 28nm and below. "We are currently evaluating going back to 40 nm," Vito said.
What information does DRC+ need to run? What's the output?
It needs a library of yield-detractor patterns and DFM rules to enforce. This comes from GLOBALFOUNDRIES. EDA tools will consume those libraries and run DRC+ in a pushbutton mode. Cadence tools that support DRC+ include Encounter Digital Implementation System, Virtuoso, Chip Optimizer, and Litho Physical Analyzer today, with Physical Verification System coming later this year.
DRC+ returns error markers. The actual output reporting varies according to the tool. For example, with Encounter, reporting is built into the Encounter browser. Encounter also provides automatic fixing of violations, and Virtuoso will offer auto-fixing in Q1 2010.
Does DRC+ limit the designer to a predefined set of "good" layout patterns?
No, it identifies patterns that should be avoided. "You can always enable more restricted rules but there are tradeoffs from an area perspective," Vito said. "DRC+ reduces the burden on designers from being restricted."
Who runs DRC+, and when in the design/manufacturing process?
DRC+ allows "in design" DFM by layout designers. "Because of its speed and high performance, it allows you to do design checking while you're doing the design, rather than running simulation late in the game," Ya-Chieh said. "Any time you run DRC, you can also run DRC+." This could occur at the standard cell, block, or full chip level.
Vito noted that DRC+ allows "full-chip DFM physical verification," which would otherwise be very difficult. Without this capability, design teams might have to fix hundreds of lithography violations.
What was the Cadence contribution to DRC+?
Cadence helped develop the pattern matching capability that is the heart of DRC+. This work actually began at a company called Command CAD, which was acquired by Cadence in 2007. The technology was key to the development of DRC+, Vito said. The collaboration began with AMD before GLOBALFOUNDRIES spun off from AMD.
How fast is DRC+?
Its performance is comparable to standard DRC. It actually scales more easily than DRC, Vito noted, because DRC adopts new advanced rules at each process node, requiring additional run-time. Additional patterns do not pose the same run-time burden for DRC+.
How can readers learn more?
Cadence and GLOBALFOUNDRIES held two recent one-hour webinars with a lot of detailed information tailored to both custom and digital designers:
These webinars will be archived here roughly a week after the dates shown above. Meanwhile, a number of free Silicon Realization webinars will be held through early December, and you can read about them here.
Conclusion: DFM will never be truly "easy," but DRC+ looks like a big improvement over previous ways of finding and fixing lithography hot spots. As such, it may speed adoption of process nodes at 28nm and below.