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Not long ago it was widely assumed that 7nm IC design would require extreme ultra-violet (EUV) lithography. But early experiments suggest that 193nm lithography can also play a role, albeit with some workarounds, restrictions, and tradeoffs, according to IBM lithography expert Lars Liebmann.
Liebmann recently gave a talk at Cadence San Jose headquarters titled “Opportunities for Physical Design Tool Innovation in Design Technology Co-optimization [DTCO] of Advanced Technology Nodes.” In the talk, he outlined a methodology for quantifying the difference between a 7nm EUV implementation and a 193i (193nm lithography) implementation. Liebmann’s presentation covered the “expanding cycles of DTCO,” including:
Liebmann cautioned that the work he presented is the first iteration for a specific scaling target, and it is focused on digital logic, not analog or memory. “It’s still a work in progress,” he said, “so enjoy the methodology but don’t focus too much on the outcome.”
Here is what Liebmann had to say about the above-mentioned cycles of DTCO.
Cycle 1: Establish Scaling Targets
Liebmann started his presentation with a basic question – what pitches are we scaling to? Just talking about 7nm or 10nm process nodes won’t help, he said, because this nomenclature is “somewhat meaningless.” But a 32nm metal pitch is about 50% of the back end of line (BEOL) pitch in a 14/16nm node, and should be about right for the 7nm process node. With a gear ratio of ¾ between metal and fins, a 24nm fin pitch should be about right. Liebmann also calculated that a contacted poly pitch of 40nm and a via pitch of 45nm are workable numbers for the 7nm node.
Liebmann also looked at cell height options based on gear ratio compliance, and determined that a 7 ½ track cell height is a suitable target for the 7nm node.
Cycle 2: Establish a Patterning Solution
“If we try to achieve these resolutions with 193nm lithography we will have to do some pretty complicated things,” Liebmann said. These complicated things include self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and litho-etch repeated three times (LELELE). EUV, in contrast, mostly uses single exposures (SE). The various patterning options all have design restrictions, from forbidden pitches and preferred orientations to unidirectional designs with very limited sets of pitches.
One way to gauge scalability is to take a look at cost, and Liebmann showed a cost chart for the various techniques. As shown at the left, a 193nm single exposure has a cost factor of 1.
Looking at this chart, a single-exposure EUV wafer would have about the same cost as a 193nm SADP wafer. Liebmann noted, however, that the numbers here “still have a lot of uncertainty” and that the process must be more mature before we can have accurate cost assessments.
Cycle 3: Establish Design Objectives for PPA Scaling
Liebmann wasn’t able to talk directly about PPA due to “sensitive issues,” but he showed a chart that cited elements of PPA cost scaling. For example, area is impacted by cell area, placement, and routing. Power and performance are factors of device width and wiring. And cost is affected by patterning.
Cycle 4: Establish the Cell Architecture
Using an inverter example, Liebmann showed layouts for a possible cell architecture. In the first example, attributes included a 2X wide M1 power rail, six M2 signal tracks, 3+ access points per pin, output pin alignment with M2 tracks, and local interconnect that straps poly fingers. Despite these “good attributes” the cell is “completely unmanufacturable,” Liebmann said. Given a cell height of 7 ½ tracks, the cell takes a lot more space than is actually available.
liebmann went through various revisions of his cell example, noting that “if we’re going to scale aggressive cell heights, you will likely see two levels of wiring used inside the cell.” He ended up with a cell that retained the attributes from the previous attempt, and could potentially work at 7nm.
After reviewing the fundamentals of SAQP, Liebmann showed a “SAQP compatible” cell architecture (below). It has horizontal M0 at 5/4 M2 pitch, vertical M1 at 5/4 M2 pitch, stapled power rail, 3 access points per pin, and horizontal M2 with 5 signal tracks. Cell height is 7 ½ tracks. There are some technical reasons why an odd number of tracks is required, but the important point is that the cell “could be patternable.” The routing in the cell is unidirectional; a bidirectional layout would require EUV.
Cycle 5: Estimate Macro-Level Scaling
Some heavily used cells take a lot of space. An example is a multiplexer, and Liebmann showed some examples of mux cells. He noted that EUV permits “special constructs” such as “cross-couple” and “handshake,” and these constructs make it possible to wire up transistors at the density designers need. 193nm lithography can’t support these constructs.
Designers don’t want to have to generate a lot of detailed cells to begin place and route. Hence the idea of “cell abstractions” that communicate the blockages, power rails, pin access points, and the basic dimensions of the cell. These abstractions also provide a basis of comparison between EUV and 193nm lithography.
Cycle 6: Estimate Routed Macro-Level Scaling
A first cycle of routing experiments quickly showed that routing congestion is going to be an issue for 193nm lithography. To put it more precisely:
Note that the 193i cell requires unidirectional routing, while the EUV cell has a preferred orientation.
Such results are not apparent until you do a full macro-level analysis, Liebmann said. “The price of getting this wrong can be very substantial. If you give up 36% of macro area just because you scaled to the wrong target, it could be quite devastating and could easily put you out of business.”
In the end, he said, designers will want to mix and match EUV and 193i stacks. “Use EUV where it counts the most, and use the rest at 193i to conserve costs,” he said. “To do that you have to understand where you can get the biggest bang for having fewer restrictions.”
Liebmann concluded by noting that there are “too many parameters” in time-consuming experiments. This includes cell height, cell width, unidirectional vs. bidirectional, straight poly connection vs. offset poly connection, and much more. “Could we improve efficiency through more automation? Could we extend EDA to automated design exploration?” he asked.
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