Get email delivery of the Cadence blog featured here
DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in three increasingly critical areas for system-on-chip (SoC) design - low power, mixed signal, and the move to a higher abstraction level with SystemC.
Following are some suggested events in each of the three areas noted above. This is not a complete conference schedule - for that, see the DVCon web site. That is also where you'll find registration information. In addition to the paid conference passes you can get a free Exhibits Only pass that includes both of the scheduled panels and the keynote speech.
Transaction Level Modeling, SystemC, and HW/SW Co-Verification
North American SystemC Users Group 17th meeting - Monday Feb. 27, 8:30 am - 12:00 pm. Speakers from Texas Instruments, Doulos, University of Paderborn, Cadence, University of Pennsylvania, Duolog. FREE registration at http://www.nascug.org/.
Town Hall Lunch with Accellera Systems Initiative - Monday 12:00 pm - 1:00 pm. Stan Krolikoski of Cadence, Accellera Systems Initiative secretary, will host this open meeting to answer the question, "What will success for the Accellera Systems Initiative look like?"
Last year's Accellera - OSCI "Town Hall" meeting at DVCon
Tutorial: An Introduction to IEEE 1666-2011, the New SystemC Standard - Monday 1:30 pm - 5:00 pm. John Aynsley of Doulos gives a detailed view of the revised standard.
Co-located Meeting: Hardware/Software Co-Design from a Software Perspective -- Monday 6:00 - 8:30 pm. Sponsored by EDAC Emerging Companies Committee.
Session 3: SystemC and Beyond - Tuesday 9:30 am - 11:00 am. Papers from University of Paderborn, PMC-Sierra, and Paneve LLC.
Session 7: Verification and Debugging Tips - Wednesday 8:00 am - 10:00 am. Includes Cadence paper on memory debugging of virtual platforms with TLM 2.0.
Panel: Build or Buy - Which is the Best Practice for Hardware-Assisted Verification? Wednesday 3:30 pm - 4:30 pm. Brian Bailey moderates this panel on emulation and FPGA-based prototyping. Panelists from Qualcomm, ARM, SpringSoft, Xilinx and Cadence discuss the tradeoffs between these solutions and the pros and cons of purchasing versus building in-house.
Low-Power Design and Verification
Session 1: Low Power Techniques - Tuesday 9:30 am-11:00 am. Charles Dawson of Cadence moderates the first conference session with presentations from Mentor Graphics, Cadence and Synopsys. Cadence paper focuses on low-power equivalence checking.
Cadence Sponsored Lunch - Earn Your Degree in the Low-Power Arts and Sciences. Tuesday 12:30 pm - 2:00 pm. Cadence and user experts will lead verification engineers and managers in a lively low-power discussion.
Poster Session 1 - Tuesday 10:30 am - See Cadence papers on "PSL/SVA assertions in SPICE" and "New challenges in verification of mixed-signal IP and SoC design."
Session 6: Mixed-Signal Verification - Tuesday 11:00 am - 12:30 pm. Papers from Maxim/Cadence, Infineon, Mentor Graphics. Maxim paper provides a case study of applying UVM-MS to a complex mixed-signal SoC design.
Session 8: Getting to Coverage Closure - Wednesday 8:00 am - 10:00 am. Includes Cadence paper on "Bringing continuous domain into SystemVerilog covergroups."
And Wait - There's More
More traditional verification topics (I'm including "formal" in this category) will also get thorough coverage at DVCon. Here is what you can expect.
Monday Feb. 27 features a full day of Universal Verification Methodology (UVM) tutorials, an introduction to the Unified Coverage Interoperability Standard (UCIS), and a tutorial on verification automation using IP-XACT.
Tuesday Feb. 28 includes sessions on UVM Techniques, Verification Benchmarking, and Formal Techniques. Exhibits run 3:30 - 6:30 pm. Speakers for a "Big Wigs" panel at 2:30 pm had not been publicized at the time of this writing (check back here).
Wednesday March 1 includes sessions on Verification and Debugging Tips, Coverage Closure, UVM in a Multi-Platform World, UVM Stimulus Generation, Verification Case Studies, and SystemVerilog Tips and Techniques. The keynote address will be given by Aart de Geus, Synopsys CEO. Exhibits run 4:30 - 7:00 pm.
Thursday March 2 concludes the conference with half-day tutorials on formal analysis "apps" (sponsored by Cadence), verification of multi-core SoCs, leveraging formal verification throughout the design cycle, and verification IP productivity.
See you at DVCon!