heard about the escalating costs of system-on-chip (SoC) development. But what
are the costs, and what are the potential savings? Steve Glaser, corporate vice
president of strategic development at Cadence, filled in some of those numbers
at a keynote speech March 24 at the International Symposium on Quality
Electronic Design (ISQED).
talked about both design costs and unit costs, and identified "best practices"
that can help reduce both. He also discussed the cost of delay (getting to
market late) and the cost of failure (such as respins). "We're dealing with the
exploding costs of design and trying to get to the point where we can create a
very predictable and profitable chip design industry," he said.
First, the bad news
presented some information about design and unit costs. It comes from various
sources, including customers and analysts:
The good news - best practices can
unit costs can be significantly managed by bringing "best practices" into IP
creation and SoC integration early, Steve said. Some specific suggestions are
Finally, some good numbers
provided a few examples of the time and cost savings that are possible through
good design techniques:
One of my
more popular blog postings last year suggested that SoC development costs are chronically
underestimated. If that's the case, the kind of information that Steve
presented in his keynote can only help.