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Jasper Design Automation had leading-edge formal verification technology before its acquisition by Cadence this summer. A picture of how this technology fits into the Cadence system verification flow emerged Nov. 10, 2014 at a keynote speech at the first Jasper User Group (JUG) conference held since the acquisition.
The keynote session had two speakers. The first was Charlie Huang (right), Executive Vice President of the System and Verification Group, and Worldwide Field Organization, at Cadence. His talk was aptly titled “Formal—A Critical Component of the Cadence System Development Suite.” The second speaker was Oz Levia, general manager of the new Formal and Automated Business Unit at Cadence.
Cadence is clearly thinking big when it comes to formal verification. Huang noted that formal plays a role throughout the system development cycle; helps with simulation, emulation, and debugging; and brings about automation that can help reduce verification cost and time. Levia said that Cadence now has the largest formal R&D team on the planet. He also noted that Cadence will use the Jasper platform to deliver formal verification in the future.
Automation Reduces Verification Costs
Huang cited industry data showing that system on chip (SoC) development costs are rapidly rising, mostly due to verification and embedded software. But most EDA money is spent on implementation, not verification. As a result, implementation is highly automated, but that hasn’t happened yet for verification. “This is an area of opportunity for Cadence,” Huang said. “So, we decided to invest aggressively in formal.”
Formal verification “is not just another new tool in the toolbox,” Huang said. Formal techniques can “inject” other aspects of verification with intelligence, making the overall verification cycle smarter. Formal can help make simulation, emulation, and debugging more efficient. And formal technology can help throughout the SoC and system development cycle, from early stage IP selection all the way to post-silicon debug.
Huang noted that verification requires a “hierarchy” of tasks, including block-level design and verification, subsystem-level design and verification, SoC-level design and verification, and bare-metal software validation. “We see ourselves extending these technologies into things like hardware/software co-development and co-verification,” he said.
Fueled by 20% year-over-year growth for formal technology, Jasper has seen rapid growth in recent years and has high visibility within key Cadence customers, Huang said. Meanwhile, Cadence has also played a role in developing formal verification technology. The combination of Cadence Incisive formal technology and Jasper formal technology will be a “great addition” to the Cadence verification portfolio, he said.
“Formal verification will become a central part of the Cadence verification arsenal, together with simulation, emulation, prototyping, and virtual platforms,” Huang said. As such, it’s a good fit with the Cadence System Development Suite, a set of interconnected hardware and software development platforms introduced in 2011. The diagram below shows that Jasper and Cadence formal verification technology is an important part of the integrated Cadence verification solution.
Formal and Automated Business Group
Levia (left) said that the Formal and Automated Business Group is “by far the largest formal team, with more than 100 R&D engineers spread all over the world.” The group has five global R&D centers, over 20 people with formal PhDs, over 30 dedicated field specialists, and over 80 AEs trained worldwide.
Both Cadence and Jasper have developed compelling formal offerings. What’s the difference? Levia said that Jasper was targeting “sometimes difficult to solve” automated formal apps, all joined together with the Jasper Visualize GUI. Cadence Incisive Enterprise Verifier (IEV) and Incisive Formal Verifier (IFV) have been focused more on integration with simulation, metric-driven verification, and coverage.
“Our plan going forward is to use the Jasper platform as a vehicle to deliver all this value, and more, into the future,” Levia said. “We will combine the value of IFV and IEV into this platform. So far integration is proceeding on schedule. We’ve had very good feedback from customers.”
Not long ago formal tools were difficult to use, Levia noted. That’s not the case today. “If you look at where formal is today with adoption by many companies, by customers in large and small companies, we have definitely crossed the chasm,” he said.
The JUG conference ran Nov. 10-11, 2014, in Santa Clara, California. It included 10 user presentations, two morning keynote sessions, and several Cadence presentations, including a product and technology roadmap. Two lunches were followed by verification product demos. A live blog feed is available for the keynote sessions at the conference.
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