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The Common Platform Technology Forum held March 14 in Santa Clara, California, provided an updated look at process technology, design challenges, and ecosystem collaboration at 28nm and below. Much of the content is available throughout 2012 as part of a Virtual Technology Forum. Following is a report on one presentation, "Delivering on 20nm and Embarking on 14nm," given in the virtual forum by Samta Bansal (right), senior product manager for Silicon Realization at Cadence.
The presentation offers a good overview of design challenges (or "discontinuities") at 20nm, and a peek into the collaboration already underway for the 14nm node. It shows how Cadence is working with Common Platform partners, including Samsung, IBM and GLOBALFOUNDRIES, to resolve challenges at both of these upcoming nodes.
First of all, who is going to move to 20nm and why? The move is driven by consumer demand for smaller form factors, higher performance, and lower power. Compared to 28nm, Bansal noted, 20nm can provide 30-50% better performance, 50% area reduction, and around 30% power savings. These are compelling attributes for applications such as mobile computing, smartphones, wireless, servers, entertainment systems, and more.
"But 20nm performance doesn't come for free," Bansal noted. "A lot of effort from EDA vendors, foundries, and silicon realization teams will be needed." And that's what the rest of the presentation is about.
Impacts of Double Patterning
The most-discussed 20nm issue is double patterning, which is required when wiring pitches drop below 80nm. "The concept of double patterning is simple," Bansal said. "Simply split the design layers with structures that are too close together to resolve with 193nm lithography into two separate masks, expose each mask separately, and the geometries produced on the wafer will be what was originally drawn."
What's not so simple is the implementation. Double patterning impacts layout and physical verification, and imposes new design rules that must be integrated into automated tools. It requires additional design for manufacturability (DFM) capabilities, such as litho-friendly design simulation, and places new requirements on parasitic extraction.
More specifically, Bansal said, a placement engine must be able to either read double patterning information embedded in standard cells, or to colorize cells on the fly to produce a placement that is double-patterning correct. During routing, a correct-by-construction approach is needed to avoid design rule and colorization conflicts. Finally, there is usually a slight offset between masks, and this produces capacitance variation that needs to be modeled and analyzed.
It's Not Just Double Patterning
But 20nm challenges go far beyond double patterning. For example, smaller nodes bring thinner gate oxides. And more and more customers are using multiple power domains, potentially with high voltages for some applications. "Designers will need to rigorously check their circuits to avoid structures that result in delayed electrical failures," Bansal noted. Also, she said, variation is becoming so extreme that simple "guard banding" no longer works.
One of the main reasons to move to 20nm is to design larger chips, and design flows must be able to support them. Bansal noted that 32/28nm chips today are reaching transistor counts of 8-16 billion, which suggest that there may be 32 billion transistor chips at 20nm. What is needed, she said, is "a design methodology that is self-correcting, prevention-based, and automated, enabling designers to fix problems early on."
20nm design isn't just about digital implementation. "It is critical for any 20nm solution to support a mixed-signal environment," Bansal said. Further, standard-cell and IP design must take 20nm process rules and double-patterning requirements into account. For these reasons the Cadence 20nm solution includes both custom/analog and digital implementation:
Bansal noted that Cadence has also been working with its partners on a linked custom/digital/packaging technology that includes 2D, 2.5D with silicon interposer, and 3D-IC capabilities.
Common Platform "proof points" for the Cadence 20nm methodology include a 22nm silicon-on-insulator test chip taped out with IBM, and a 20nm ARM Cortex-M0 test chip taped out with Samsung.
A Look Ahead to 14nm
"We are working on 14nm now because it takes 3-4 years to just understand the challenges and plan for them before it can be widely adopted," Bansal said. She observed that 14nm will involve new technologies such as FinFETs, and said Cadence is working with Common Platform partners on data model enhancements, design rule development, and assessment of restricted design rules.
The partners are also exploring the impact of process variability, a double-patterning flow for 14nm, and correct-by-construction IP development. There's an "intensive consultation" on ground rule choices and the impact on physical design, especially routing, Bansal said. Early experiments are exploring the impact of cell design on performance, area, and wiring.
While 20nm brings "discontinuities" in design and manufacturing, Bansal concluded, Cadence has enough experience with ecosystem collaboration, test chip proof points, and customer success to be "confident" 20nm will be successful.
To view the presentation, register for the Virtual Technology Forum here, go into the virtual conference area, and look for the 3pm presentation under the "Agenda" tab. You can also view keynotes by IBM, Samsung, and GLOBALFOUNDRIES.