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Semiconductor startup Soft Machines believes its Variable Instruction Set Computing (VISC) CPU cores will represent a bold leap forward for computer architectures. In a presentation at the Front-End Design Summit held at Cadence San Jose headquarters in December 2014, now available in video, Soft Machines engineering managers showed how physically-aware synthesis fits into the semi-custom design methodology behind the VISC processor cores.
The product of a seven-year “stealth” technology development, the VISC microprocessor architecture promises to revive performance-per-watt scaling and to significantly boost performance and power. The architecture is based on the concept of “virtual cores” and “virtual hardware” threads, and it allows dynamic allocation and sharing of resources across cores. Soft Machines has working 28nm silicon and is working on smaller geometries. (For more information about VISC, see the Soft Machines website).
Raj Khanna, vice president of engineering for CPU hardware at Soft Machines, started the presentation by defining several different types of synthesis for IC design:
As a processor company, Khanna pointed out, Soft Machines has people who do manual pipelining and develop micro-architectures by hand. “Physical synthesis influences the logic algorithms, not so much the micro-architecture,” he said. “But internal to the pipeline stages, we have a tremendous impact on the actual architecture.” He added that “what we’re seeing with smaller geometries is that congestion and wire availability have a tremendous influence on the actual architecture.”
So what’s possible with physically-aware synthesis? “Nice, square, regular structures, especially for high-performance datapaths,” Khanna said. Structures are thus predictable and layout friendly. Another plus is that module architectures can be more thoroughly optimized for size, aspect ratio, wiring availability, and more. These features have a tremendous impact on the architecture. Example: The Kogge-Stone adder is very fast, but it has congestion issues in one direction, so if you don’t have the right physical dimensions in the wiring, it is probably a bad choice.
Double patterning is needed for advanced process nodes. As a result, Khanna said, 10 layers of silicon actually provide fewer routing resources than 10 layers in the past. Many of the upper layers don’t get used very well. “What we would like to do is take the congestion awareness in the structuring of the original netlist, and push more of the wiring into the upper layers, which are much faster,” he said.
Khanna said that the gap between front-end and back-end designers has actually grown. This is because the industry moved to an IP-centric model where one company designs IP and many companies implement it. Designs that once had 20K flip-flops may now have 500K flip-flops. “We see an opportunity for physically-aware synthesis to extract the performance from the technology by using higher-level concepts, being more floorplan-driven and more wiring-driven, and using the tools to do the bottom-up architecture of blocks so it fits within our top-down scheme,” he said.
The Cadence Front-End Design Summit drew a large crowd
Physically-aware synthesis has implications for IP handoff. Hard macros, Khanna noted, have good PPA but are technology dependent. Soft macros are technology independent but the PPA is not as good. “We see the possibility to create something we call a ‘gel macro’ that could be much more technology independent and more top-down driven,” he said. “With the use of physical synthesis from the bottom up, it can be very well mated to the user’s technology.”
Te-Chen Tsai, staff design engineer, talked about some of Soft Machine’s experiences with tools using physically aware synthesis. He related an example in which a floorplan was badly congested and pretty much not routable. “After that, we turned on physically aware structuring, and it just solved our problem,” he said. “And not only about congestion, but also timing. It’s very close to what we would expect from a semi-custom design.”
Both a slide presentation and video are available for the Soft Machines presentation, in addition to other Front-End Design Summit presentations. A Cadence Community log-in is required—quick and easy registration if you don’t have one. Soft Machines will also present at the CDNLive Silicon Valley Conference on March 10 and 11, 2015.
- Front-End Summit: Avoiding Routing Congestion with High-Level Synthesis
- Front-End EDA Panel: “Empowering” the RTL Designer
- Technology Summit: Deep Insights into Synthesis, Verification, and Test
- Front-End Design Summit: How to Get the Best Results from Physical Synthesis