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EDA tools are traditionally intended as “one size fits all” offerings. With the complexity of today’s electronic systems, however, there’s a need for more vertical solutions that are aimed at specific applications and/or processors. A case in point is the Cadence® system verification solution for ARM® based SoC designs, a customized offering that provides fast software/hardware verification, performance analysis, and power and performance optimization tailored for mobile and multimedia applications that use the 64-bit ARM v8 architecture.
In this interview Ziv Binyamini, corporate vice president and CTO for the Systems Verification Group at Cadence, talks about the verification solution, the challenges it addresses, the tools and capabilities it includes, and the tradeoffs it allows.
Q: Ziv, what’s your job responsibility at Cadence?
A: I’m responsible for solutions that span multiple products, such as the Incisive® and Palladium® XP platforms and verification IP. I focus on SoC solutions, most specifically on multi-core SoCs that use the 64-bit ARM v8 architecture. Today this includes the ARM Cortex®-A57 and ARM Cortex-A53 processors.
Q: How long have you been at Cadence, and where were you before then?
A: I came to Cadence from Verisity 10 years ago, when Cadence acquired Verisity. I was at Verisity for seven years. Before that, I was in verification technology at Intel for nine years.
Q: Cadence has lots of tools for system-level design and verification. Why do we need an optimized solution for mobile and multimedia SoCs using the 64-bit ARM architecture?
A: These applications make up the biggest segment of the EDA customer base. Almost all of the SoCs in these areas use the ARM architecture. In order to bring a more complete and advanced solution for customers, we decided to provide not just tools but solutions that are highly optimized for the challenges that customers will face.
Q: But why develop a solution for the ARM v8 architecture? Is this widely used in mobile devices today?
A: Let me give you some quick background. ARM engineered the 64-bit v8 architecture, and announced it three years ago, in order to grow into the server market. The v8 architecture was not really aimed at mobile. Meanwhile, suppliers of mobile and multimedia semiconductors were developing dual-core and quad-core 32-bit CPUs.
When Apple announced their 64-bit iPhone5 last year, they shocked the whole market. Everybody said, “who needs 64 bits for mobile?” At the same time, semiconductor suppliers were starting to announce multi-core CPUs for mobile applications. Now many of the major mobile SoC providers have moved to 64-bit architectures with up to 8 cores.
We [Cadence] serve this inflection point by providing solutions that are specifically targeted to SoCs for mobile and multimedia applications.
Q: What are the main design and verification challenges for developers of 64-bit multi-core SoCs for mobile devices?
A: Challenges include software, verification for multiple cores, power and performance optimization, and integration.
There’s a much bigger software stack for mobile SoCs, which need to be verified early in the design cycle – preferably before silicon is back. Multi-core verification brings with it all sorts of coherency and concurrency problems. To test concurrency, you need to verify that software is running in parallel. You need to write C language tests that run concurrently on all these processors. Writing such tests manually is a nightmare.
As for integration, there is a lot of hardware IP, software IP, and verification IP. You have to create many different configurations to verify all these together – it’s a lot of labor-intensive work. Optimization for power and performance – in terms of bandwidth and latency – is really hard. Finally, you have to make use of different tools to perform verification, validation, analysis, and software bring-up.
Q: What does the ARM system verification solution include?
A: The general solutions we have developed include Virtual System Platform (VSP) for transaction-level modeling integrated with ARM Fast Models, the Incisive Enterprise Simulator (IES), the Palladium XP acceleration and emulation environment, Protium™ FPGA-based prototyping, and our Verification IP catalog. These are part of the System Development Suite. On top of that, we have built specialized capabilities for ARM-based SoC designers. One of these solutions is the Palladium “hybrid” emulation model. Here users run ARM Fast Models in VSP on the workstation, where they can run at 100MHz or more, and put the rest of the SoC into the emulator.
On Oct. 1, 2014, Cadence announced that ARM had achieved a 50X faster OS boot-up time on Mali™ GPU development using the hybrid mode with Palladium XP and ARM Fast Models [press release here]. This is really a game changer for system validation and it is needed pre-silicon.
Dynamic power analysis with the Palladium is another specialized tool that can be applied to ARM mobile and multimedia SoCs. This lets users analyze power using a real application. Cadence had a dynamic power analysis capability prior to the verification solution for ARM-based SoCs, but it’s been improved to meet the unique challenges of getting the right power.
Interconnect Workbench is another tool in the ARM SoC flow. It’s a solution that allows you to verify the interconnect of your SoC. It also allows a very early performance analysis with a cycle-accurate model. The first thing customers get excited about is the performance analysis. They all benefit from the fully automated flow that allows them to build complex interconnect testbenches, automatically saving 8X in productivity.
We also have a very broad portfolio of verification IP targeted to ARM SoCs. We have VIP for AMBA® protocols and Cortex-A protocols. We have a variety of ways to speed simulation performance. Finally, we are working on additional solutions that have not been announced yet for other challenges.
Q: The 50X speedup in hybrid mode sounds exciting, but what is the real benefit?
A: The hybrid mode allows the customer to bring up the full software stack, and to boot Android in 30 minutes or so. This is hard to do with FPGAs because the capacity of an FPGA is not large enough. Using multiple FPGAs in traditional FPGA-based prototypes requires a largely manual, time-consuming setup to get the desired speed. We have addressed the setup time vs. performance trade-offs with our Protium rapid prototyping system, which is adjacent to Palladium.
However, if you can bring an existing Palladium design together with Fast Models and boot an OS very early, you can run thousands of software regression tests before you tape out. Traditionally customers do this type of work when silicon comes back, but with the hybrid mode in emulation they can do it much faster, and develop software before silicon. They can take the time to really ensure the quality of their software.
Q: What do customers actually get with the verification solution for ARM-based SoCs?
A: We customize and optimize each solution for an ARM-based SoC so that each one is a completely good fit, coming with all the models that are necessary. Each solution is different. If the customer didn’t have this level of customization, things would be really complicated. It would take a long time to make the flow work and they could not extract the full benefit. That’s why we work closely with our customers to get our solutions up and running and fully optimized to their specific needs.
Related Customer Success Story
NVIDIA offered a presentation titled “Palladium for Android SW Validation, GPU Testing on ARM v8 SoC” at the Cadence Theater at the Design Automation Conference (DAC 2014). An audio recording with slides is available here. No registration is required.
Related Blog Posts
Cadence Interconnect Workbench – A Cycle Accurate Approach to SoC Performance Analysis
Designer View – How Emulation/Virtual Prototyping “Hybrid” Speeds Software Development
Palladium XP II – Two New Use Models for Hardware/Software Verification