Get email delivery of the Cadence blog featured here
The Global Semiconductor Alliance (GSA) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries, outsourced assembly and test (OSAT) providers, and other important ecosystem players can come together and work through the business and technical challenges posed by 3D-IC technology.
Ken Potts, product marketing director at Cadence, recently became the chairman of the GSA 3D IC Working Group. In this interview he talks about the business and technical challenges facing 3D-ICs, the role of the GSA working group, the advantages of 3D-ICs, the need for standards, and when 2.5D and 3D-ICs will come into volume production.
Q: Ken, what do you do at Cadence and how did you come to chair the GSA working group?
A: I'm very involved with strategic alliances in emerging technology areas. I'm involved in the Si2 [Silicon Integration Initiative] OpenAccess and OpenPDK coalitions, and I chair the Si2 Low Power Coalition, where we're pushing low power up into the systems space.
I started out as an engineer, and I've been involved on and off with 3D-ICs in my career. I was actually on a big 3D-IC project for the government, under DARPA, back in the mid-1990s. I like this area of technology and I was up to speed on it, so it made sense for me to get involved.
Q: What does the GSA 3D working group do?
A: GSA is interesting because it's not really a standards body per se. Their focus is more on business intelligence. They write papers, they create a forum for discussion, and they explore some of the challenges. I think this particular [3D] working group will go a little bit beyond that in terms of objectives and deliverables. 3D-IC technology crosses a lot of domains, and to make it a reality, there are some significant business challenges we need to address. I think GSA is uniquely positioned to help us work through some of that.
Q: What do you see as the key business challenges right now?
A: What we're dealing with is a very integrated technology across design, manufacturing and test, but it has to be applied in a disintegrated chain. Significant pieces of the technology are in separate companies, so now the question becomes, who's responsible for what. If I design this 3D chip and the foundry manufactures it and somebody else does assembly and test, and I have a part failure, who do I talk to? And then, if I'm the OSAT or the manufacturer or the EDA vendor, and I had a hand in creating value, how do I get paid for that?
Q: There are also still some questions about the manufacturing flow, such as who puts in the TSVs [through-silicon vias] at what stage of the process.
A: Right, and that will be impacted by the business solution that comes along. If you're in an integrated environment, then you can always go with the best technical solution, and figure out the right time in the process to insert the via. But when you have business boundaries in there, you may be making business tradeoffs and sub-optimizing the technical solution. Right now everyone is jockeying for position because they can see that 3D-IC is going to be ultimately required to meet product requirements for power, performance, and form factor.
Q: What do you see as the key technical challenges for 3D-ICs?
A: I think there are some huge challenges in terms of power density. You're getting a huge level of integration, but what are you going to do with all that energy that's now combined into a smaller space? I think there are some real challenges in the test domain - how do you test and isolate errors? And then, along with the power density, we have thermal-mechanical interactions. It's a whole new physical realm and it can't be just EEs figuring this out; we'll need help from mechanical engineers too.
These issues will require early exploration. If I consider planar, 2.5D, and 3D implementations, what are the business tradeoffs for me? What do my yields look like? What do my power and performance look like? EDA vendors have to step up to the plate with early planning tools, with floorplanning and analysis tools, and finally, in the back end, with design for test.
Q: How can the GSA working group help resolve some of these technical and business challenges?
A: First we can help by getting a shared understanding of what the challenges are. It's not clear to me that the OSAT, the manufacturer, and the EDA vendor all have the same view of what the business model looks like. I think GSA can be an agent for that understanding, so there's going to be some education that happens there. If we can get a consensus on a shared understanding of the problem and the solution, then we can help the industry move in a coherent direction rather than getting into unnecessary, counter-productive battles.
Q: So what's the big "win" for 3D-ICs? Is it power, performance, or area?
A: Integration is number one, but 3D-ICs will also allow designers to achieve a given memory bandwidth at a much lower power. The reason is that 3D interconnect greatly reduces the parasitics to system memory. Due to the reduction of parasitics, you can see significant performance improvements at the same power level, or you can keep the same performance level and really reduce the power.
I think wide I/O is going to be a key driver; it plays very nicely with 3D ICs. In fact Cadence has done a couple of 3D-IC wide I/O projects, and we'll see more of that, I'm sure. (Note: A 2011 Industry Insights blog post reports on one of those projects).
Q: When do you think we'll see volume production of 2.5D and 3D-ICs?
A: I think by 2013 we're going to have volume production in 2.5D. But I think there are a lot of issues to be sorted out before we get into mainstream production of full 3D TSV based designs. Of course there are stacked memories out there already, but I'm talking about full integration of an SoC with vertical integration of memory and other functional elements. For that, volume production could be as early as 2014 depending on how some of the challenges are addressed.
Q: What's needed in terms of standards for 3D-ICs?
A: There is a need for standards in those areas where there would be no competitive advantage, where everyone would have to reinvent the same things, and there's no value created. The GSA can help by refining the problem statement, and showing where the opportunities for innovation are, and where the opportunities for standardization are.
Q: And finally, what is Cadence's interest in 3D-IC technology?
A: Cadence has taken a leadership role in this technology area for quite some time. We have done 8 testchips and 1 production chip covering various 2.5D and 3D scenarios and applications on 3D TSVs. The SiP [silicon in package] activity that we've had for many years is where we really started to look 3D from packaging angle.
About 6 years ago we started extending this into IC stacking where TSVs were incorporated to stack ICs. We partnered with leading customers and foundries to develop our tools and methodologies around this. We've done a lot of development work on 3D-IC and we really believe that now is the time the industry has to get on that path. Today we're involved in the standards side, and we're working with the GSA to help accelerate the adoption.
We think it's very early in the technology and there is tremendous opportunity for innovation. We're participating because there are things we can do in the industry to help make 3D-ICs a reality.
(Note: The GSA 3D IC Working Group has published a 3D-IC Design Tools and Services Tour Guide, as well as a report on the benefits and barriers to 3D-IC adoption. For more information, click here.)