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Last year Cadence acquired Forte Design Systems, a pioneer of high-level synthesis (HLS) and provider of the Cynthesizer SystemC-based synthesis tool. This week (Feb. 24, 2015) Cadence released the Stratus High-Level Synthesis Platform, a new HLS product that combines the “best of both” from Cynthesizer and the Cadence C-to-Silicon Compiler HLS tool. In this interview, Sean Dart and Phil Bishop explain what’s behind the Stratus platform, and provide a general update on HLS.
Dart (right) was the former CEO of Forte Design Systems, and today is senior group director for R&D in the System Verification Group at Cadence. Bishop (below, left) was until recently the vice president of the System Verification Group, and he now heads North America Central sales at Cadence.
Q: Until recently, Cadence and Forte were independently selling HLS tools. Why merge two tools into one?
Dart: The general approaches of the two products were similar, but each had its own unique features and technologies. We feel that, when combined into a single product, these capabilities will give us more than a 2X improvement in business.
Bishop: Cadence did a lot of analysis before purchasing Forte. We liked a lot of things, including the complementary nature of the customers. Both Cadence and Forte did a brilliant job of getting into some places that were really difficult. What was fascinating to us was how complementary, and yet disparate, the customer bases were.
Another plus is that Cadence and Forte combined had a number of people who understood HLS very strongly. Finally, there was some really strong technology in areas like pipeline usage, power optimization, and visualization. When you couple those together, it just makes sense on multiple levels.
Dart: Now that we’re not competing with each other and we’re spending that energy serving customers, we’ll get to one plus one equals more than two.
Q: How does Stratus represent the best of Cadence and Forte? Can you speak a little about what each company contributed to the new combined product?
Dart: A lot of the core synthesis algorithms are a mix of the two. There were optimizations in both tools that were very appealing. Otherwise, there are a few key things that are easy to identify. Stratus uses interface IP and floating-point IP from Forte. The IDE [Integrated Development Environment] for SystemC code comes from Forte Cynthesizer. The analysis GUI and the ECO capability come from [Cadence] C-to-Silicon Compiler.
Bishop: C-to-Silicon Compiler had [Cadence] RTL Compiler under the hood, as does the Stratus platform. That really opens up the rest of the Cadence design flow and allows HLS to be the front end for physically aware synthesis.
Q: The Stratus platform also has an integration with RTL Compiler Physical (RCP). How does that work?
Dart: We can take any RTL micro-architecture that’s generated by the Stratus platform all the way through RCP and collect congestion information. Then we can back-annotate that congestion information into the original SystemC, and point out code constructs in your original design that may cause congestion problems in your RTL.
[Note: for more information about HLS and routing congestion, see this blog post from the Cadence Front-End Design Summit.]
Q: Is the Forte CellMath floating-point library part of the Stratus platform? How does it work?
Dart: Yes. In your SystemC code, you just declare floating-point variables and write C++ code that uses floating-point operations. Based on the technology libraries, the tool will automatically infer various floating-point operations and instantiate those into the design. It’s almost completely automatic.
Q: How do you think the Stratus platform compares to the competition? What’s unique?
Dart: I think the most obvious capabilities are the ECO capability, the ties to RCP, the floating-point capability, and the SystemC IDE.
Bishop: I would also cite the link into physical design. The depth, quality, and proven nature of the ECO handling is unique for us. And it’s not just ECOs on the front end, it’s the back end, too.
Q: How does the ECO capability work?
Dart: If you make changes to SystemC, you rerun synthesis in a mode that takes the original generated design as the reference design, and attempts to keep the new version as close to the original version as possible. Changes require only very minor modifications to the RTL. This mode can support late changes.
Q: Taking a broader look, who’s using HLS these days?
Dart: Anyone who’s a “who’s who” in the electronics industry. It crosses a very broad range of applications. HLS is commonly used for video and image processing applications and wireless communications, as well as automotive, consumer, and medical applications.
Bishop: Users of HLS tend to have designs that are algorithmically rich. This may include DSP, imaging, or networking. It’s all digital in nature.
Q: What challenges remain with HLS?
Bishop: We’re getting into implementation a lot more. Physically aware aspects are becoming more and more important. We have to look at physical effects like power, area, and timing. Then we have to look at things like testability. That’s the next level of implementation we have to address.
And then on the verification side, we’re trying to lift customers up to SystemC usage. You can run your designs a lot faster than at RTL, so more and more customers are signing off at the SystemC level. I think these two areas [physical implementation and verification] will absolutely explode the HLS market and make it far, far larger than it is today.
Dart: It’s kind of a side issue, but some customers grow so fast in their use of HLS that they are having trouble finding educated and experienced staff. They have to train and educate people into how HLS works.
Q: Is any more standards work needed, and if so what?
Dart: I think there will be an evolution of the standard. Currently, there is work on a synthesizable subset of the SystemC language. All of the synthesis tools right now have distinct input styles. I expect the industry will push towards standards.
Q: What do customers see as the primary benefits of HLS?
Dart: There is certainly a benefit to creating and maintaining your IP in a more abstract form. You create more quickly, it’s easier to modify in the future, and the productivity gain you get when you retarget the IP is very, very significant. Customers can quickly create more valuable IP that has a longer shelf life.
Bishop: Another major benefit is verification productivity. By moving to higher level, TLM [transaction-level modeling] simulation models, you can move through verification more quickly. Another advantage is that HLS allows unique optimizations for power, performance, and area. We have generally been beating hand-coded results, and the time it takes you to get to a design with power, performance, and area requirements met is a lot faster.
Q: So wrapping up, what’s the impact of the Stratus platform?
Dart: I don’t think there is any other HLS tool that has the depth and breadth of features and capabilities that the Stratus platform has.
Bishop: I think it’s unique in the industry. The features that have been brought together are unique. It’s the first time that one of the big EDA guys has been behind an HLS tool all the way from SystemC to the back end.
Note: Further information about Stratus is available at this landing page.
Related Blog Posts
- Sean Dart Q&A: Former Forte CEO Discusses Past, Present, and Future of High-Level Synthesis
- Front-End Summit: Avoiding Routing Congestion with High-Level Synthesis
- How Cadence Acquisition of Forte Boosts High-Level Synthesis