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It's easy to be confused by the alphabet soup of acronyms that surrounds static timing analysis (STA). At the Signoff Summit at Cadence headquarters on Nov. 21, 2013, Igor Keller, senior R&D architect at the company, explained several on-chip variation (OCV) approaches that provide some of the advantages of statistical STA (SSTA) without its relatively high costs.
Ten years ago, as I well remember, SSTA was poised to become one of the next big things in IC design. It made sense. Rather than returning a single timing number, SSTA could return a statistical distribution. It could tell you, for example, that you have an 80% chance of hitting a given timing number. But the development of SSTA libraries proved to be a stumbling block.
"Statistical timing is a great approach," Keller said. "It's the most accurate I can think of, but it's also the most expensive. Except for IDMs, nobody could really deploy it in production because it required too much run time and memory."
Alternatives to SSTA
Keller reviewed several approaches for handling in-die variations at advanced nodes, starting with plain old OCV analysis. OCV provides a single derating factor for all instances. Results can be grossly optimistic or pessimistic. As Keller noted, you may not be able to close your timing without leaving a lot of performance on the table.
Keller noted that the distinction between local and global variations is very important with OCV. You can handle global variations with corners (best case, nominal, and worst-case combinations) but corner analysis is very difficult with local variations. These variations "do not correlate statistically, and they have a profound effect on OCV," he said. "The biggest challenge in OCV variations today is handling the local uncorrelated variables."
Advanced OCV (AOCV), sometimes referred to as location-based OCV (LOCV), is aimed at reducing pessimism. It provides variable derating for min/max, cell, arc, and stage count. Libraries can be created from existing SSTA characterization tools. The graphic below shows the OCV and AOCV derates compared to an "ideal" derate.
AOCV, however, assumes similar statistical variability between cells regardless of slew and load. It can still be very optimistic or pessimistic compared to SSTA. "You cannot assume that all your instances on the path are the same cells," Keller said. "You cannot assume that all the input slews are the same. People realized that you cannot really reduce pessimism a lot with AOCV." In particular, he said, stage count is a "flaky number" that can generate a lot of pessimism.
Keller had relatively little to say about parametric OCV (POCV), other than its elimination of stage count as a parameter. It represents one more step towards SSTA but still does not resolve the delay dependency on slew and load.
Statistical OCV in the Sweet Spot?
Statistical OCV (SOCV) is a simplified approach to SSTA that uses a single local variable. It solves the major limitations of AOCV, including variation dependency on slew and load, and the assumption that the same cell, or load, is in the path. It promises near SSTA accuracy for a small additional cost of runtime and memory compared to AOCV, and it can include signoff-accurate signal integrity (SI) analysis.
"You handle global variations by going to corners," Keller said. "The corner based approach is well understood by engineers. At the same time, you push the tricky part of the variation - which is local variation - into statistical. You compress everything into one variable and that's your statistical OCV."
Keller said that SOCV is a "version of SSTA which is not as expensive as statistical timing, yet is almost as accurate." SOCV also has a "look and feel" that is familiar to users of STA. Users who want to see a single flat timing number report, as they would for STA, can continue to do so. SOCV can also provide a three-sigma statistical distribution for those who want to see it.
According to Keller, SOCV is much more accurate than AOCV, especially for graph-based analysis AOCV. The SOCV timing flow is very similar to the "regular" timing flow. SOCV can be validated with SPICE Monte Carlo analysis.
In conclusion, Keller said, "SOCV brings you advantages over other approaches by doing a more accurate analysis in terms of dependency on slew and load." It's a proven technology, he said, and automated flows exist for library generation.
So, maybe full SSTA wasn't the "next big thing" in IC design after all - but it has clearly inspired some new and more accurate approaches to timing analysis.
Note: This was one of a number of presentations in the day-long Cadence Signoff Summit, which also included updates on the Cadence Voltus IC Power Integrity Solution, Tempus Timing Signoff Solution, signoff extraction, incremental metal fill, path-based timing analysis, physical verification signoff, and design for manufacturability. Presenters included Cadence R&D experts and customers. Presentations will be archived online at a later time.