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Perhaps the most challenging question about 3D-IC design is what gets done when, by which kind of provider. With its recently introduced chip-on-wafer-on-substrate (CoWoS) process, TSMC has taken a step towards clarifying what the 3D-IC ecosystem might look like. And Cadence helped refine the methodology and provided design tool support, as announced today (June 4, 2012) at the Design Automation Conference (DAC), where Cadence and TSMC are offering a joint tutorial on 3D-ICs.
CoWoS came to light in March with the announcement of an Altera test vehicle developed using this process. TSMC defined CoWoS as "an integrated process technology that attaches device silicon chips to a wafer through a chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided."
Technically, the CoWoS process produces what is sometimes called a "2.5D" IC. Instead of stacking dies on top of each other, it mounts heterogeneous dies on a silicon interposer substrate. By using through-silicon vias (TSVs), this arrangement provides huge power and performance advantages over traditional wire-bonded packages. A CoWoS test module is on display at the Cadence booth (#1930) at DAC, as shown at right.
What is most significant, however, is that TSMC developed a methodology that allows the company to manufacture 2.5D ICs entirely in-house, without using outsourced assembly and test (OSAT) providers or other third parties. John Murphy, director of strategic business alliances at Cadence, noted that previous silicon interposer modules have required multiple companies. "Now TSMC has taken ownership of the whole process, which means they're a step away from being able to support [stacked] 3D IC," he observed.
Manufacturing a 2.5D silicon interposer module is challenging. For example, TSVs - which are extra-large vias - must be placed to take into consideration the stresses that will be placed on the interposer during assembly. The wafers must be thinned to about 100 microns to expose the TSVs, and then the chips are mounted on the interposer to make a module. There's a risk of breaking those wafers after thinning.
Also, testing of the chip-to-interposer interfaces posed one of the most significant challenges to ensure that the micro-bumps formed electrically sound connections. TSMC accomplished all this, assembled the modules, and has proven they can achieve acceptable yields to make the technology commercially viable, Murphy noted.
Cadence helped TSMC develop two early CoWoS test modules. For example, Murphy said, "we worked with them around bump alignment. Bumps are really small and they have to be aligned to the interposer. The chip can be an SoC or any kind of functional chip. Bumps have to be aligned and co-designed between the interposer and the chip so you get the proper locations and follow design rules."
Cadence enhanced several product lines with this co-design support including Encounter Digital Implementation System, the Virtuoso custom/analog platform, and the Allegro Silicon-in-Package (SiP) product. These tools were used to design the test modules. Further, the Cadence 3D-IC methodology now provides multi-chip co-design support through TSV floorplanning, micro-bump alignment, placement, routing, chip/package/board co-design, IR drop analysis, extraction, verification, and design for test.
With the TSMC CoWoS process and Cadence EDA tool support, volume production of 2.5D interposer modules is close at hand. And with volume production of full stacked-die 3D-ICs still some ways off, the interest in 2.5D is keen. "Every 20nm customer has a product planned within the next two years using this technology," Murphy said.
Enough Talk! Let's Go to the Tutorial!
To learn more about the experience and knowledge that TSMC and Cadence have gained, join the companies in a DAC tutorial titled "Enough Talk! Practical Approaches to 3D-IC - TSV/Silicon Interposer and Wide I/O Implementation From People Who Have Been There and Done That." This tutorial will be presented Monday, June 4 at 8:30-10:30 am and then repeated at 11:30 am-1:30 pm and again at 3:30-5:30 pm. Presenters are Frank Lee, director of the Design Methodology Division at TSMC, and Marc Greenberg, director of product marketing for DDR DRAM Design IP products in the SoC Realization group at Cadence. For information, click here.
Meanwhile, Cadence is offering the following demos at booth 1930:
Realizing 3D-IC Design Using an Integrated IC Design Solution - Monday 10:00 am, Tuesday noon, Wednesday 9:00 am
Exploring 3D-IC Using IC Package-Driven Silicon Interposer Technology - Tuesday 5:00 pm. Wednesday 10:00am
For a listing of all Cadence DAC booth demos, click here.