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Custom/analog designers working at FinFET process nodes are going to need all the help they can get. As announced by Cadence today (July 8, 2013), TSMC will help out by providing native SKILL-based process design kits (PDKs) for the TSMC 16nm FinFET process. TSMC is also expanding its usage of the Cadence Virtuoso platform to design its own semiconductor IP.
SKILL is a programming language that is used to develop PDKs and PCells (parameterized cells), and is also widely used by customers to customize Cadence tools including the Virtuoso custom/analog and Allegro PCB design platforms. The first 16nm PDKs that TSMC issues will include SKILL-based PDKs.
PDKs link process technology to design, and are an essential part of any foundry-based IC design and manufacturing flow. The diagram below provides an overview of what PDKs contain and how they interact with design tools.
According to Steve Lewis, product marketing director at Cadence, the native SKILL PDKs will unleash the full power of Virtuoso for 16nm design. PDKs, as he explained, contain basic transistors and design rules. But there's also a layer on top of those elements that "has to be able to trigger tools to do the right thing." For non-SKILL PDKs, this layer will typically be written in Tcl, which is different from the language used by the tools, resulting in a disconnect and preventing deeper customization. For SKILL PDKs, this layer will be written in SKILL, providing direct access to Virtuoso.
Specifically, the SKILL PDKs will allow designers to take full advantage of Virtuoso's advanced layout and routing features, including those in the January 2013 Virtuoso Advanced Node release. This release provides such capabilities as color-aware double patterning, "partial layouts" that account for layout-dependent effects, and new local interconnect routing layers. The new PDKs will also enable features such as auto-alignment, automatic handling of design rules during abutment, chaining devices, and advanced routing. "Customers will not have to do a lot of tinkering to use these advanced features," Lewis said.
Lewis noted that there's an exponential explosion of design rules at 16nm. These include a number of positioning rules that depend on the layout context. With the SKILL PDKs, he said, 16nm design rules "will be understood by our router right out of the box. The native SKILL PDK allows the tools to read those rules, digest them, and direct the customer to avoid violating rules as they're doing the layout."
Finally, Lewis noted, TSMC's use of Virtuoso for its own IP benefits Virtuoso users. TSMC and Cadence have cooperated to develop a flow that is proven through TSMC's IP development and silicon. There is also more security for Virtuoso users. "You're using the tool that your foundry provider used to develop the PDK, and that the foundry provider is using for their own designs in their own fab," Lewis said. "If TSMC believes in [Virtuoso], then you as a customer should, too."
Further information is available here.
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Introduction to Cadence Virtuoso Advanced Node Design Environment
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