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The 10nm FinFET semiconductor process node is coming up sooner than you might expect! Two technical presentations at the recent TSMC Open Innovation Platform (OIP) Ecosystem Forum Sept. 30, 2014, provided a good overview of the design and process development challenges of the 10nm node, and presented some solutions from an ongoing collaboration between TSMC and Cadence.
In a keynote speech Mark Liu, president and co-CEO of TSMC, said he expects 10nm customer tapeouts in the second half of 2015 and risk production in the fourth quarter of the year. “Our goal is to enable customers’ product ramp in 2016,” Liu said. “To meet this goal we have to get the 10nm design ecosystem ready.”
In a second keynote speech Cliff Hou, TSMC chief technologist, said that the 10nm node will enable designs that have 2.2X the gate density of 16nm ICs and are 25 percent faster while consuming 45 percent less power. (For more information on the TSMC OIP keynotes, see this blog post from Brian Fuller).
Several days before the TSMC OIP Forum, Cadence announced that Cadence and TSMC are collaborating on support for TSMC’s 10nm FinFET process, and that Cadence EDA solutions are ready to support early customer design starts at 10nm. At the same time, Cadence announced that its digital and custom/analog tools achieved TSMC certification for the 16nm FinFET Plus process (you can read the press release here).
Process Development and RC Extraction
One of the 10nm technical sessions was titled “10nm FEOL/MEOL Challenges and Process Development with Parasitic RC Extractions.” This session looked at front end of line (FEOL) and middle end of line (MEOL) challenges in parasitic extraction, and highlighted the use of the Cadence Quantus QRC Extraction Solution for 10nm process development. It also discussed SRAM development, which is the key to any new process IP development.
Sean Lee, deputy director of design methodology at TSMC, noted that the most challenging aspect of MEOL parasitic modeling and model-based capacitance extraction is the introduction of 3D FinFET transistors (right). Because the FinFET is a 3D structure, he explained, there are more parasitics to extract, such as fringing capacitance from the gate and fins, gate to source, gate to drain, and coupling capacitance with local interconnects.
Here are some other 10nm process development FEOL/MEOL challenges:
On the back end of line (BEOL), Lee noted, double patterning is mandatory. The sequence in which nets are colored may create slightly different extraction results, and extraction tools must take this into account. That means coloring needs to be done before extraction in order to get the most accurate results.
Due to this demand for tight accuracy, Lee said, some engineers may be drawn to 3D field solvers. But the time that it takes to run a 3D solver is generally impractical. Lee showed the following chart, which illustrates that 3D solvers run orders of magnitude more slowly than 2.5D solvers – up to 4000X slower in one case.
What’s needed, therefore, is close-to-3D accuracy at 2.5D extraction speeds. It’s a combination TSMC has found in Quantus QRC Extraction Solution. Lee mentioned an example in which a VCO extraction took three weeks with a full 3D solver and a few minutes in a Cadence flow using Quantus QRC –and produced a netlist about 2X smaller than the competition.
Lee showed a portion of the 10nm Certification Report for Quantus QRC Extraction Solution and pointed to tight correlations to the 3D “golden” value. These numbers are based on critical nets taken from a real design. For example, here are the correlations for MOS capacitance:
Core: mean=-1.2%, 2-sigma=2.6% IO: mean=-1.7%, 2-sigma=1.8% SRAM: mean=-0.6%, 2-sigma=0.6%
Lee also demonstrated how Quantus QRC Extraction Solution gained accuracy over various generations of the TSMC 16nm FinFET process, from DRM (design rule manual) v0.05 through v1.0. “Between the different generations we’ve been able to tune accuracy very close to a 3D field solver,” Lee said. The full data isn’t in yet for 10nm – the current DRM version is v0.05 – but Lee expects to have the same kind of success.
Hou Ji, engineering group director of Cadence, gave the second part of the presentation and discussed SRAM development. SRAM density, she noted, is used as a metric to measure how successful you’ll be at the next process node. To achieve the highest possible density, “you need to use a very compact wiring structure,” she said. “That requires a very accurate RC model to help predict the parasitic impact on the circuit. You need field solver-like accuracy, fast performance, and an accurate and efficient production engine.”
In simulating 10nm SRAM cells and macros, Ji said, Quantus QRC Extraction Solution had a maximum timing error of 5%, achieved a faster runtime than competitors, performed an RC reduction with a 0.4% maximum accuracy penalty, and generated a netlist 1.5X smaller than competitors. She also noted that Quantus QRC Extraction Solution runs 3-4X faster than competing solutions given the same number of CPUs and the same number of corners. Beyond that, Quantus QRC is scalable to hundreds of CPUs. Finally, Ji noted that Quantus QRC Extraction Solution offers inductance extraction for the transistor and cell levels.
Design Challenges at 10nm
Another TSMC OIP Forum presentation was titled “Tackling coloring, cell pin access, variability, and late stage ECOs for TSMC 10nm with Cadence Encounter.” Rahul Deokar, product manager at Cadence, opened the session by noting that “we have early 10nm readiness, and we have a flow available for early customers to try out.”
Deokar showed the following slide to demonstrate design challenges at 10nm. He noted that 10nm is the second generation FinFET node and the second generation double patterning (DPT) node. The biggest change for designers, he noted, is that coloring is mandatory at 10nm – no longer can this task be left for the foundry. What’s needed, in fact, is a full coloring flow that extends from place and route to extraction and design rule checking (DRC).
Designers will also encounter an “explosion” in the number of design rules, a resistance increase on wires and vias, and a resistance variation of up to 50% for different color tracks. “Generally the requirement for accuracy goes up tremendously,” Deokar said. “As a result, the ECO part of the flow is very critical.”
To get ready for 10nm, Deokar said, Cadence worked with TSMC on the following issues:
"One thing that becomes relevant and required at 10nm is statistical analysis, extraction, timing, and OCV-driven optimization,” Deokar commented.
To support 10nm designs, the EDI System offers a correct-by-construction color-driven implementation flow. This flow avoids coloring conflicts, and has a massive parallel capability for avoiding rule conflicts. The flow includes GigaPlace (right), the EDI System’s next-generation placement engine. GigaPlace includes an analytical placement engine that offers more accuracy than heuristic approaches. It is color aware, exploits massive parallelism, considers pin access, and is tightly integrated with the Cadence GigaOpt optimization engine and with the Tempus Timing Signoff Solution.
Meanwhile, the Cadence NanoRoute software supports all 10nm routing rules, offers enhanced pin access support, and handles “fat” M2 pins, a new 10nm requirement. It can handle a fixed color methodology where users define color masks in the cell library, Deokar noted.
Ruben Molina, product manager at Cadence, finished the presentation by talking about ECO automation. Cadence provides ECO solutions that address both functional and timing ECOs, including such tools as the Cadence Encounter Conformal ECO Designer, Encounter RTL Compiler with Physical, and the Tempus solution. ECO flows are important, he said, because signoff closure has become a key bottleneck, and one reason is that timing closure typically requires many iterations.
Physically aware optimization is important but not sufficient. “With the new 16nm and 10nm design rules, you really have to know whether cell abutment or pin access is an issue,” Molina said. “It’s not sufficient to just have a space to put a cell. You really have to know all the design rules associated with placing that cell.”
“There has been a doubling of design rules from 28nm to 16nm, and it’s just going to get worse at 10nm,” Molina concluded.
Related Blog Posts
TSMC OIP Forum: 16nm FinFETs, 3D-ICs Gain EDA and IP Support (Oct. 7, 2013)
2014 TSMC Technology Symposium: Full Speed Ahead for 16nm FinFET Plus, 10nm, and 7nm (April 28, 2014)
Cadence Tools, IP Enable First Production TSMC 16nm FinFET System on Chip (Oct. 1, 2014)