Google FeedBurner is phasing out its RSS-to-email subscription service. While we are currently working on the implementation of a new system, you may experience an interruption in your email subscription service.
Please stay tuned for further communications.
Get email delivery of the Cadence blog featured here
The 10nm semiconductor process node is no longer in the distant future – it is here today, according to presenters at the recent TSMC 2015 Technology Symposium in San Jose, California. TSMC executives noted that EDA tools have been certified, most of the IP is ready or close to ready, and risk production is expected to begin in the fourth quarter of 2015.
The good news is that scaling still works. Due to aggressive scaling, the 10nm FinFET (10FF) process node increases logic density by 2.1X compared to the TSMC 16nm FinFET Plus (16FF+) process node. Compared to 16FF+, the 10FF node can offer a 20% speed increase at the same power, or more than 40% power reduction at the same speed. TSMC has demonstrated a fully functional 256Mb SRAM in 10FF technology with die size scaling close to 50% of 16FF+.
However, 10FF will require some changes in the IC design flow. The main difference is that, due to the need for more double patterning, everything must be color-aware – including all the tools and the designers. 10FF is the first process node that requires color assignment on the part of chip designers. Meanwhile, conventional litho-etch, litho-etch (LELE) double patterning doesn’t produce the best solution at 10nm, giving rise to a “spacer” technology that is a little more complex.
Here are some more details about 10nm at TSMC as presented in talks by Dr. Cliff Hou, vice president of R&D at TSMC (right), and Dr. BJ Woo, vice president of business development at TSMC (below left). At the TSMC Symposium, speakers also introduced two new process nodes, 16HHC and 28HPC+ (see blog post here).
The Tools are Ready
Launching an advanced process node takes a collaborative ecosystem that includes EDA and IP providers – and TSMC has been working on the 10nm node for several years with that ecosystem. According to Hou, TSMC has finished the certification of EDA tools for 10FF, along with the development of foundation IP and most of the critical interface IP. (Note: Cadence announced just prior to the TSMC Symposium that its digital and custom/analog tools have received TSMC certification for the most recent 10nm FinFET Design Rule Manual and SPICE models. A press release has further details.)
To make sure EDA solutions really work, TSMC built a “product like” 10FF validation vehicle. It’s actually a system on chip (SoC) that includes an ARM Cortex-A57 quad core. Hou said the chip taped out a couple of weeks prior to the Symposium.
10FF is the first TSMC node that requires designers to do color, so the design flow is “a little different,” Hou said. There are a few other things to keep in mind. These include a high drive current in the FinFET devices, and an increase in metal resistance. IR drop must be analyzed and electromigration (EM) is more of a problem. Finally, Hou said, “10nm design rules are a little more complicated than before.”
TSMC developed a 10FF color-aware custom design solution with its partners. It includes schematics, layout, dummy insertion, verification, RC extraction, and EM and IR analyses. Each of these steps is color-aware. Designers can assign color in the schematic, and it will carry over to layout. TSMC provides a utility that can compensate for color changes, and also provides a real-time, on-the-fly design rule checker.
TSMC and its partners also developed a color-aware ASIC design flow. Features here include color-aware macro auto placement, color-aware standard cell placement, routing on pre-defined color tracks, color-aware RC extraction, routing optimization, and color-aware vias. Finally, TSMC and its partners developed a color-aware signoff flow. This includes design rule checking (DRC), layout vs. schematic (LVS), RC extraction, SPICE and Fast SPICE, and static timing analysis (STA).
“If tools are not covered, let us know,” Hou said. “We will work with our partners.” He added that TSMC expects to finish most of its 10FF IP offerings by the second half of 2015. Thanks to process, tool, and IP readiness, he said, “10nm is ready for design starts at this moment.”
More Aggressive than Moore
According to Woo, TSMC is not only keeping up with Moore’s Law – it is running ahead of the law with its 10FF offering. “We have done a lot more aggressive scaling than Moore’s Law demands for our 10nm technology,” she said. A case in point is the fully functional 256Mb SRAM with a cell size that is approximately 50% smaller than the 16FF+ cell size. She called this an “exceptional shrink ratio” that goes beyond traditional scaling.
And it’s not just SRAM. The 10FF node, Woo said, can scale key pitches by more than 70%. Combine that with innovative layout, and 10nm can achieve almost 50% die size scaling compared to 16FF+. “And this is very, very aggressive,” she said.
After noting that the 16FF+ already provides “clear performance leadership,” Woo said that 10FF offers a 22% performance gain over 16FF+ at the same power, or more than 40% power reduction at the same speed. This comparison is based on a TSMC internal ring oscillator benchmark circuit. For the Cortex-A57 test chip used to validate EDA tools, the result was a 19% speed increase at the same power, and a 38% power reduction at the same speed.
New features in 10FF include a unidirectional (1D) layout style and new local interconnect layer. These features help 10FF achieve a 2.1X logic density improvement over 16FF+, whereas normally TSMC gets about a 1.9X density boost for node migration, Woo said. In addition to the density improvement, the 1D Mx architecture can reduce CD (critical dimension) variation by 60%, she said.
10FF requires double patterning, but TSMC does not use not the relatively simple litho-etch, litho-etch patterning that is used at 20nm and 16nm. The problem with LELE, Woo said, is that overlay changes can result in variation in the line space. While this is tolerable in 20nm and 16nm, at 10nm this variation will translate into a very small metal space. That can result in an immature dielectric breakdown. Thus, TSMC 10FF uses a self-aligned spacer process that assures that uniform metal line spacings are maintained.
Another 10nm challenge is that resistance goes up significantly as metal layers scale down. Selectively relaxing the metal pitch provides a way to optimize performance versus density. 10FF allows the designer to make this kind of adjustment in order to find the best tradeoff.
Leakage control is another issue that TSMC has addressed. In the 10FF node, TSMC offers three choices for transistor threshold voltage, helping designers optimize for speed and leakage. Woo also noted that 10FF I/Os run at 1.8V, but it is possible to under-drive to 1.0V to support the LPDDR4 interface.
In summary, Woo noted, most of the commonly used tools have been certified for 10FF, and a “very complete IP list” is already available with process design kits (PDKs). The bottom line is that you can start your 10nm design now.
Related Blog Posts
Moore’s Law “Not Slowing Down” – TSMC Executive
TSMC Symposium: New Low-power Process, Expanded R&D Will Drive Vast Innovation: TSMC executive
TSMC Symposium: New 16FFC and 28HPC+ Processes Target “Mainstream” Designers and Internet of Things (IOT)
Photos from Taiwan Semiconductor Manufacturing Co., Ltd