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As the world’s largest pure-play foundry, TSMC pioneers advanced process nodes for leading-edge semiconductor design companies. At the recent TSMC 2015 Technology Symposium in San Jose, however, much of the emphasis was on the “mainstream” part of TSMC’s roadmap, where TSMC introduced two new processes – 16nm FinFET C (16FFC) and 28nm HPC+.

16FFC is a “compact” version of the 16nm FinFET+ (16FF+) process technology that is now in risk production at TSMC. It claims advantages in power, performance, and area compared to the existing 16FF+ process, along with easy migration from 16FF+. It can be used for ultra low-power IoT applications such as wearables, mobile, and consumer.

28HPC+ is an improved version of the 28HPC (High Performance Compact) process, which is itself a fairly recent development. Late last year 28HPC went into volume production, and it provides a 10% smaller die size and 30% power reduction compared to TSMC’s earlier 28LP process. 28HPC+ ups the ante by providing 15% faster speed at the same leakage, or 30-50% reduction in leakage at the same speed, compared to 28HPC.

TSMC also provided updates on other processes on its roadmap, which includes the following:

• High Performance – 28HP, 28HPM, 20SoC, 16FF+
• Mainstream – 28LP, 28HPC, 28HPC+, 16FFC
• Ultra Low Power – 55ULP, 40ULP, 28ULP, 16FFC (16FFC is in both mainstream and low power categories)

Additionally, TSMC executives offered a detailed look at the upcoming 10nm process node and the EDA and IP ecosystem that has grown up around it. The message is that 10nm is ready for design work, with risk production later this year. 10nm will be discussed further in a forthcoming blog post.

16FFC: Cost and Power Reduction

Dr. Mark Liu, TSMC President and Co-CEO (right), announced 16FFC in his keynote speech. He said that 16FFC has cost and power reduction advantages that “mainstream” markets demand. “By reducing nominal voltage to 0.55V, 16FFC reduces power consumption by over 50%, meeting power requirements for smart phones, consumer products, and wearables,” he said. Liu noted that 16FFC tapeouts are expected in the second half of next year. (For complete coverage of Liu’s keynote speech, see Brian Fuller’s blog post).

Subsequent speakers filled in some details. Compared to the current 16FF+ process, said Dr. Cliff Hou (left), vice president of R&D at TSMC, 16FFC simplifies the process, reducing manufacturing cycle time; reduces SRAM area; optimizes die size; tightens SPICE corners; and can run below 0.6V to support ultra-low power. It also reduces leakage. “Even with all those enhancements, the design will still look the same,” he said.

To migrate to 16FFC, standard cell designers will need to re-characterize their libraries for power, performance, and area optimization. TSMC will offer new, optimized SRAM compilers. I/Os will not be changed from 16FF+. For analog and interface IP, TSMC recommends that users run SPICE simulation to check margins and re-characterize as needed.

Hou said that 16FFC will go into risk production in 2016. By the end of 2015, TSMC will provide foundation IP with fully characterized corners. All interface and analog IP will be finished by the second quarter of 2016. Design rules remain the same as in 16FF+.

According to Dr. BJ Woo (right), vice president for business development at TSMC, the company will continue to “tighten the process corners” to further reduce the die size of the 16FFC process. The goal, however, is “to be as close to 16FF+ as possible, to minimize the impact to existing IP.” TSMC is also working to simplify the 16FFC process with mask layer reductions.

Woo said that TSMC has been working with its ecosystem partners to ease migration from 16FF+ to 16FFC. The result, she said, will be “the best 16nm performance and the most cost-effective solution for the mid- to low-end market. 16FFC will be the most power-efficient solution for ultra low-power wearable devices and IoT applications.”

28HPC+: Better Power and Performance

Hou introduced the 28HPC+ node by citing its advantages over the current 28HPC process. 28HPC+, he said, provides 15% faster speed, better SRAM speed and leakage, smaller device corners and mismatch, better analog properties, and smaller back-end of line (BEOL) Mx corners. It is also more compact with its 7-track and 9-track cell libraries.

“Even with this kind of advancement, the design rules stay the same,” Hou said. “You don’t need to redesign the layout.” As is the case for 16FFC, designers who move from 28HPC to 28HPC+ will need to re-characterize the standard cell library and run SPICE simulation. I/Os stay the same, and TSMC will provide a new SRAM compiler.

Hou said that 28HPC+ foundation IP will be ready in Q2 of 2015, and interface IP will be ready at the end of 2015.

Woo noted that the 28nm node is going into its sixth year of technology production at TSMC. She said the company introduced 28HPC last year as a way of bringing CPUs up to 2GHz speeds. “28HPC+ can allocate more power budgets to push the CPU performance, such that you can significantly increase the speed to be over 2GHz at the same power budget,” she said. “In mobile devices, faster CPU speed leads to a much better user experience.”

Compared to 28HPC, Woo said, 28HPC+ offers a 15% performance gain at the same leakage, and can achieve an additional 30% performance gain “as a signoff condition.” That means speed is measured at a slow-slow corner and leakage is measured at a fast-fast corner. Woo noted that designers can replace low Vt 28HPC transistors with comparable 28HPC+ transistors, and can reduce leakage by up to 80% for a high-speed circuit.

Process Updates

TSMC executives cited impressive progress with the 16FF+ process node, noting that it has received over 12 tapeouts so far and that a total of 50 tapeouts are expected for 2015. Compared to the 20SoC node, 16FF+ uses 50% less power at the same speed, or provides a 40% speed gain at the same power. According to Y.J. Mii, vice president of R&D at TSMC, 16FF+ yield is already approaching 20SoC yield. He said 16FF+ provided better maturity at risk production than any previous TSMC process.

On the low-power side, TSMC last year announced 55ULP, 40ULP, and 28ULP processes, all of which support processing speeds up to 1.2 GHz. The devices are aimed at the IoT and wearable device markets. “This is the most powerful platform for you to attack the emerging IoT market,” Mii said.

Finally, don’t count 20SoC out. That process node, which uses planar transistors, is a “great success,” according to Woo. She said that 20SoC experienced the fastest ramp in TSMC history, 5X faster than 28nm was at the same point in time.

Richard Goering

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• Moore’s Law “Not Slowing Down” – TSMC Executive
• TSMC Symposium: New Low-power Process, Expanded R&D Will Drive Vast Innovation: TSMC executive
• Digital Advanced Node

Photos from Taiwan Semiconductor Manufacturing Co., Ltd