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Using traditional analog solvers for top-level, mixed-signal SoC simulation is inefficient and impractical. Intrinsix, a design services firm, recently evaluated an alternative solution called real number modeling (RNM). This solution makes it possible to use real numbers in a digital simulation, letting engineers model analog circuits at near-digital speeds. RNM support in the Cadence Incisive platform includes the wired real (wreal) data type defined by Verilog-AMS.
In this interview Ron Airey, principal verification engineer at Intrinsix, talks about his company’s experience in using RNM for a sigma delta modulator (SDM) SoC. The SoC included sigma-delta data converter IP from Intrinsix, as well as digital filters and a DSP block.
Q: Ron, what are your primary challenges with mixed-signal SoC verification?
A: The problem we have is that the analog and digital parts of the design are tested standalone. Our challenge is to develop an integrated mixed-signal verification environment that would allow us to test the SoC at the system level, and verify the interconnect between the analog and digital boundaries. It will give us a lot more confidence that we can have the full SoC tested before it’s handed off to the engineers who are routing the chip.
Q: What’s the drawback of testing analog and digital blocks separately?
A: A lot of times we’ll have signals that go between the [analog/digital] boundaries. There could be clock domain crossings. Control signals could go back into the analog portion. If you don’t have a fully mixed-signal verification environment, you can’t test the full system.
Q: How have you been verifying digital blocks?
A: We take a digital serial output from the analog simulation, capture that in a file, and use that as input stimulus to the digital portion. We can completely test the functionality of the digital side with that approach. But a couple of things are missing. One is top-level testing of the whole SoC. Also, we’re sort of limited by how many input files we have. When we rely on files from the analog guys, we have to ask them to re-run long, long simulations. If we had a model for the analog portion, we could do runs of randomly constrained input stimulus through the analog model.
Q: What’s the advantage of the RNM approach?
A: Instead of using in-line real values in SystemVerilog, I can capture the whole model in a single module and reuse it across projects. One of the most interesting things for me was the ability to do port declarations on the module itself. We couldn’t do that with SystemVerilog.
Q: What about the speed of simulation?
A: That’s a very big advantage. Before, we were relying on the analog guys to feed us digital files resulting from long simulation runs on the analog side. Now we’re completely in the RTL event-driven simulation realm. It’s a clear win.
[Note: Information provided by Intrinsix states that an SDM simulation that would take three hours with Verilog-A, or three days at the transistor level, runs in under 10 minutes on the Incisive Enterprise Simulator using Verilog-AMS wreal modeling.]
Q: Can you control the entire mixed-signal simulation from the digital testbench?
A: Yes, absolutely.
Q: Why use wreal as opposed to real data types?
A: Port declarations are one of the big differences. You can’t use real as a port declaration on a module. I also thought I’d be able to take advantage of using wreal with multiple drivers, but in this case we don’t have multiple drivers.
Q: Where are you going from here?
A: We see [RNM] as one approach to solving our problems. We’re certainly going to explore others.