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Broadcom uses a lot of memory in its video processing ICs, and that causes a simulation bottleneck, according to Normando Montecillo, senior principal engineer at Broadcom. But the company has found a better way - using formal verification and assertions to develop a new flow for verifying memory wrappers.
At the June 2011 Design Automation Conference (DAC) User Track, Montecillo and Darrow Chu of Cadence presented a paper titled "Exhaustive verification of large number of memory wrappers using formal techniques." This paper described the use of the Cadence Incisive Formal Verifier (IFV) and assertions to provide complete proofs for memory wrappers.
In the video interview below, Montecillo discusses the difficulties of using simulation for memory wrappers, the advantages of formal verification, the flow that Broadcom uses for memory wrapper verification, and the use of assertions in the flow. While it wasn't possible to simulate all the memory wrappers, he notes, formal model checking can verify all the wrappers "in a very reasonable amount of time." Today Broadcom is looking for more areas where formal might apply, Montecillo said.
This is an excellent real-world example of how formal verification can make a seemingly intractable verification problem much, much easier.
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