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Monte Carlo statistical simulations are crucial for predicting and improving yields in custom/analog IC design, but run times are becoming unwieldy at advanced process nodes. As described in a recently archived webinar, Cadence and TSMC collaborated to develop a new technique that can provide a performance improvement over statistical simulation using traditional methods.
The new method, developed for the TSMC 16nm FinFET Plus (16FF+) process node, uses a “worst sample search” approach. Basically, TSMC has developed an API that makes it possible for the Cadence Virtuoso Analog Design Environment (ADE GXL) to run sensitivity analysis using a single variable. The sensitivity analysis identifies critical devices. Designers can then run re-ordered samples to identify those most likely to fail, and find the worst cases among them. An “auto-stop” feature in ADE stops the overall sequencing when statistical yield percentages are met.
In the webinar, Jason Chen, design methodology and service marketing manager at TSMC, noted that Cadence and TSMC have a long history of collaboration over many process generations. At 16nm and below, the need for collaboration is stronger than ever, and as such, the new statistical simulation method is one of the deliverables for the TSMC 16FF+ custom design reference flow.
The growing impact of variations is driving the need for statistical simulation, Chen noted. However, designers are running into the following challenges:
TSMC, therefore, is proposing a solution that offers fast sensitivity analysis, fast statistical result estimation, increased capacity for large circuits, and an ability to change the simulation order of Monte Carlo samples. The solution is Variation-API, and it provides an interface between TSMC device variation information and the Cadence variation analysis flow.
Variation-API serves two major functions. The first is statistical variable reduction, which makes it possible to analyze a single variable instead of a set of statistical variables. The second is Monte Carlo sample re-ordering, which allows the user to run samples to find the ones that most likely to fail first.
“A design typically starts with many statistical variables to be handled,” Chen explained. “TSMC’s Variation-API is able to intelligently reduce them to a single delta Vth variable instead of many statistical variables.” After sensitivity analysis with ADE, he said, “Variation-API reorders Monte Carlo samples to identify the simulation runs that are most likely to fail first, and also finds the worst cases.”
Variation-API is tightly integrated with the ADE environment. “Users simply launch the Cadence ADE environment, which will include TSMC’s Variation-API and a Cadence toolbar,” Chen said. “Users do not have to worry about connecting two different flows.” The capability is available with the Process Design Kit (PDK) GEN2 from TSMC and Cadence Virtuoso ICADV12.1 and above.
The second part of the webinar consists of a demo by Lorenz Neureuter, product engineering manager at Cadence. The design is an op amp in TSMC 16FF+ technology, and the end goal of the simulation is to improve the yield of the circuit.
In the demo, Neureuter walks through all the major steps in the worst sample search method, starting with sensitivity analysis that varies a single parameter at a time. At the completion of a sensitivity analysis run, a results table automatically opens, and users can sort any column to identify the most important contributor for a given specification (in the demo, for example, 36% of the phase margin variation can be attributed to pin PM2).
The worst sample search method, Neureuter said, is “used to identify the worst sample per specification out of a total of N, without simulating all N samples. We can then create statistical corners based on these worst samples. Worst sample search is a sample re-ordering method. This means Monte Carlo simulations are performed in the order of probability to fail instead of the normal random order.”
“The run begins simulating the re-ordered samples, and automatically stops when there is confidence that the worst sample has been identified,” Neureuter said.
In conclusion, Neureuter said, the number of mismatches for mismatch sensitivity analysis can be reduced by 6X at 16nm in the demo. Critical devices can be identified much more efficiently. And users can achieve an order of magnitude simulation reduction in verifying yield or creating worst-case sample statistical corners.
To access the webinar, click here. A Cadence log-in is required (quick and easy registration process if you don’t have one).
- Archived Webinar: Variation-Aware Analysis for Advanced Node Design