Get email delivery of the Cadence blog featured here
3D ICs with through-silicon vias (TSVs) promise tremendous power, cost, and size advantages, but they also generate a lot of concern about what's required in terms of design flows, skills, and tools. A new Cadence whitepaper (click here to read) sets the record straight by taking a balanced look at design challenges and requirements for 3D ICs with TSVs. The whitepaper will be distributed at the RTI 3D IC conference Dec. 8-10 in Burlingame, California.
The whitepaper notes that there is no need for a new, revolutionary, 3D IC-specific design system. But there are new challenges, such as thermal management in multi-die stacks, new layout requirements, and the impact of TSVs on active devices. As a result, new capabilities are needed in such areas as system-level exploration, floorplanning, place and route, extraction and analysis, design for test, and IC/package co-design.
But first, what is a "3D IC?" Multichip modules, systems-in-package (SiPs), and stacked memory die implementations have been around for some time. What's new is the stacking of heterogeneous elements (analog, digital, and logic in addition to memory) and the use of TSVs through active layers. Eventually we will see multiple-die devices that look like this:
More specifically, here are some of the key requirements:
Because 3D IC design is multi-disciplinary, a comprehensive solution is needed. It must include early estimation and analysis, digital IC implementation and analysis, analog/mixed-signal implementation, IC/package co-design, and PCB design. 3D IC design also needs a Silicon Realization flow. EDA360 Silicon Realization brings in three capabilities - unified design intent, abstraction, and convergence with physical and manufacturing data. A successful 3D IC design environment will capture design intent up front, support abstraction with early estimation and floorplanning, and achieve convergence through test, implementation, extraction, analysis, and packaging.
Returning to the focus of my previous 3D IC blog post, the real issue is not so much technology issues as cost reduction. 3D ICs will never move to the mainstream unless they can be designed and manufactured in a cost-effective and timely way. No semiconductor company will adopt 3D ICs because the technology is "cool" (even though it is). They'll adopt the technology to make money. Design tools and flows must make that possible.