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Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility of protocols. All VIPs include highly configurable and flexible simulation models of all protocol layers, devices and transaction types. Cadence VIPs also support integration and traffic generation in all popular verification environments.
During the past year, I have seen engineers struggling with debug for VIP based simulations. The questions that bother them most are:
In this blog, I will talk about how Cadence staff and engineers are developing some app notes to help users debug using trace files. I will give you references to complete documents for following VIP - AHB, USB2.0, PCIE2.0, USB3.0, SSIC and LFPS Signaling in USB3.0.
1. AHB is a new generation of the AMBA bus that addresses the requirements of high-performance synthesizable designs. AMBA AHB is a new level of bus which sits above APB and implements features required for high performance, high clock frequency systems including burst transfers, split transactions, single cycle bus master handover, and wider data bus configurations. AMBA AHB supports a Lite version and a Regular version. AMBA AHB Lite addresses the requirements of high performance synthesizable designs. It supports a single bus master and multiple slaves. AMBA AHB Regular version supports multiple masters, multiple slaves and an arbiter to handle the arbitration between masters.
Sharath Siddappa, Lead Application Engineer at Cadence, prepared an Application Note titled Debugging AHB VIP using trace file that gives tips on how to debug AHB simulations with Cadence AHB VIP (based on PurespecTM API) from the Denali trace file. It also shows how to debug specific scenarios like reset, transactions, or callbacks.
This document will help users debug Cadence AHB VIP using trace files. It provides egrep/perl commands to extract information about various AHB transactions that would help debug failures better. The commands can be used as is by just changing the instance IDs (in bold and red) according to user's requirements. Also, the document captures commands for basic debugging. Users can combine the commands or write new commands to meet debug requirements.
2. In an Application Note titled Debugging the Trace File for USB 2.0 Verification IP, Rishubh Garg, Member of Consulting Staff at Cadence, gives you some tips on how to debug USB 2.0 simulations with Cadence USB 2.0 VIP from the Denali trace file. It shows how to debug specific scenarios like reset, suspend, resume, and packet flow.
3. Responding to the increased demand for VIP technical support and debugging documents at https://support.cadence.com/, Nikhil Sharma, Sr. Solution Engineer at Cadence, stepped up to interact with users through his knowledge-sharing documents on debugging USB3.0, SSIC and LFPS Signaling in USB3.0 with the help of trace files.
If you have ever wondered how to create, configure, and instantiate PureSpec USB 3.0 VIP in the testbench, please see Nikhil's Application Note Integrating USB 3.0 VIP and Debugging Steps Using the Trace File, and note the tips for debug using the trace file generated during simulation
4. SuperSpeed USB Inter-Chip (SSIC) defines a chip-to-chip USB based interconnect for mobile devices as well as other platforms. SSIC offers MIPI Alliance's M-PHYTM high bandwidth and low power capabilities combined with SuperSpeed USB performance enhancements. The M-PHYSM interface, a high speed serial interface, targets up to 1.2 Gbps per lane with scalability up to 5.8 Gbps per lane and offers a low pin count and exceptional power efficiency. SuperSpeed USB offers a 5.8 Gbps signaling rate per lane, up to 10 times faster than Hi-Speed USB (USB 2.0), enhanced protocol and power management and software model. Demand for higher speeds is strong in mobile consumer applications including video streaming, and SSIC fits well there.
This is another marvelous Application Note, Integrating SSIC VIP and Debugging Steps Using the Trace File, where Nikhil Sharma helps you create, configure, and instantiate PureSpec SSIC VIP in the testbench, and also provides you with tips for debug using the trace file generated during simulation.
5. LFPS (Low Frequency Periodic Signaling) in Super Speed USB is used for sideband communication between the two ports over a link. It is done when normal SS packet transmission is not possible, and "out of band" messaging is required. The Cadence Purespec USB 3.0 VIP completely supports LFPS signaling as per USB 3.0 Specifications, for various stages with timing values as defined by specifications. In Cadence VIP, these timing values are configured through propriety SOMA timing attributes through Pureview.
However, Cadence USB 3.0 VIP provides full flexibility to change these values per user requirements (for example, cutting down simulation time) along with DUT timing parameters. Most challenges faced by users around LFPS Signaling occur during link training and initialization, which are mandatory for link up. Nikhil's paper Debugging LFPS Signaling in USB 3.0 VIP using Trace File addresses a very common setup problem faced by users.
6. Last but not least, Mukul Dawar, Sr. Solutions Engineer at Cadence, compiles his knowledge in this latest AppNote, Integrating PCIE 2.0 VIP and Debugging Steps Using the Trace File. This AppNote helps users of the PureSpec PCIE 2.0 VIP from the Cadence VIPCAT 11.3 release create, configure and instantiate PureSpec PCIE 2.0 VIP in the testbench while debugging with the trace file generated during simulation.
To access the Application Notes, please login with your Cadence credentials at https://support.cadence.com/
The Cadence Online Support - https://support.cadence.com/ is your 24/7 partner for getting help in resolving issues related to Cadence software or learning Cadence tools and technologies. If you are signed up for e-mail notifications, you are likely to get notices for new solutions, Application Notes (Technical Papers), videos, manuals, and more.
In future posts I will talk more about Denali Migration Guide, NVMe Purespec VIP Usage, Verification Flow for USB, and Instantiating VIP models with SystemVerilog.