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This year, the Design Automation Conference (June 1-5 in San Francisco) has put a lot of effort into great content for IP buyers, and Cadence has great plans to highlight our IP. Here are some of the things you can see at DAC this year:
Booth 2610 demo
See Cadence's large library of IP and verification IP for memories, interfaces, analog, and peripherals. Join us for a fun-filled game and test your knowledge of the protocols used for next-generation designs. You will walk away with a greater understanding of Cadence's comprehensive IP offering. Plus, you'll have the opportunity to win fabulous prizes!
Chip Estimate booth 1533 IP talks
Monday, June 2 - 2:30 pm: Broad and High-Performance IP Cores—An overview of Cadence's Design IP portfolio supporting the most advanced technology nodes Tuesday, June 3 - 4:30 pm: Cadence Verification IP—A proven solution and S.M.A.R.T choice for verification Wednesday, June 4 - 2:00 pm: Broad and High-Performance IP Cores—An overview of Cadence's Design IP portfolio supporting the most advanced technology nodes
TSMC booth 1801 presentation
Wednesday, June 4, 11:30am: Cadence Design IP—Accelerating SoC adoption of new processes with proven IP
Conference sessions and presentations
Monday, June 2, 10:30am, Room 101: The Never-Ending Journey to iP Quality—The Modern IP Factory—IP Development for High Quality
Monday, June 2, 10:30am, Room 105: The Making and Selling of IP Business (Panel with Martin Lund, Cadence SVP)
Monday, June 2, 1:30pm, Room 105: Hot IP/High-Performance WiFi AFEs
Thursday, June 5, 3:30pm, Room 306: HW-SW Codesign for Computer Vision: Can we Make the Computer See? By Chris Rowen, Cadence Fellow