SoC and IP

Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A

MBhatnagar — Thu, 28 May 2026 19:00:00 GMT

Cadence has reached an important milestone in its collaboration with Intel Foundry with the successful completion of its first test chips on Intel 18A earlier this year. This achievement marks a meaningful step forward in enabling advanced, standards‑based interface IP on Intel 18A. More details about these test chips were recently shared in presentations at CadenceLIVE Silicon Valley and GOMACTech events.

As system architectures continue to evolve to support AI, high‑performance computing, and heterogeneous designs, early validation on silicon plays a vital role. This set of first test chips on Intel 18A reflects Cadence's continued investment in silicon‑backed IP readiness, providing customers with practical insight and reduced risk as they make IP decisions.

Advancing From Early Enablement to Silicon Validation on Intel 18A

The completion of these test chips represents a transition from early enablement activities into tangible silicon validation, using dedicated vehicles to exercise real interface behavior under representative operating conditions. The silicon-validated IP serves as a proof point for the GAA (RibbonFET) and back-side power (PowerVia) technology available on Intel 18A.

Yet rather than serving as a single proof point, each test chip supports ongoing learning across electrical performance, signal integrity, power behavior, and system integration assumptions. These insights feed directly back into model correlation and IP refinement, strengthening readiness well before customer designs move toward production.

This approach reflects a simple but critical principle: early silicon matters. It shortens learning cycles, uncovers integration considerations sooner, and helps ensure that IP entering customer SoCs is aligned with real‑world behavior on advanced nodes.

Key IP Enabled on Intel 18A

The test chips on Intel 18A technology bring together several cornerstone interface technologies from Cadence's IP portfolio, each aligned with the bandwidth, latency, and integration demands of modern systems.

High‑speed 112G PAM4 SerDes IP was exercised on Intel 18A as a foundation for bandwidth‑intensive AI, networking, and accelerator applications.

Figure 1: 112G SerDes PAM4 eye diagram

The test chips also support PCI Express^® (PCIe^®) 6.0 (64 GT/s PAM4) and PCIe 5.0 (32 GT/s NRZ) PHY IP operation, reflecting the continued evolution of high‑bandwidth I/O and coherent system architectures.

Figure 2: PCIe 6.0 Eye Plot

For the memory subsystem, LPDDR5 PHY IP was validated at high data rates on Intel 18A, supporting the power‑efficient, high‑performance memory interfaces required for advanced SoCs.

Figure 3: LPDDR5 8533 Mbps Tx/Rx Eye Diagram

Also demonstrated in the test chips was UCIe™ IP, including multi‑lane configurations and packaged implementations that align with emerging chiplet‑based system designs.

Figure 4: UCIe-AP 16G Eye Plot – 64 Lanes

Together, these protocols represent the interfaces that increasingly define system scalability—not in isolation, but in combination. Validating them on silicon helps ensure they operate cohesively across SoCs, packages, and multi‑die systems.

Reducing Risk for Advanced Designs

Early test chips play a critical role in helping customers move confidently onto new process technologies. With these test chips, Cadence can validate key interface behavior on real silicon, strengthen correlation between design models and measured results, and identify integration considerations at a stage when design flexibility is still high.

This silicon work complements Cadence's broader collaboration with Intel Foundry, including Design IP expansion, EDA tool enablement, and advanced packaging support. Taken together, these efforts are focused on a shared goal: accelerating time‑to‑value while reducing uncertainty for customers building next‑generation systems.

Continuing Momentum with Intel Foundry

Cadence remains focused on delivering IP that is not only standards‑based but backed by real silicon validation. The completion of the first test chips on Intel 18A represents an important milestone—one that reinforces Cadence's long‑term commitment to enabling customers with reliable, production‑ready IP as they move onto Intel Foundry technologies. Meanwhile, Cadence is continuing its collaboration with Intel Foundry on Intel 18A-P and Intel 14A technology nodes.

Learn more about Cadence Design IP.

Beyond PCIe Compliance: Why Stress Testing Is Crucial for Edge AI Deployments

Joe C — Thu, 14 May 2026 04:30:00 GMT

Passing PCI Express (PCIe) compliance is different from being ready for the field. A PCIe link can clear every test in a controlled lab environment and still develop margin problems six months into deployment. That’s because a compliance traffic generator isn’t designed to replicate real-world operating conditions, such as thermal stress, electrical noise, and the kind of bursty inference traffic that arises from edge AI systems constantly scaling power and performance. While compliance provides assurance that the design meets the specification, it doesn't tell you how much margin remains before it disappears once the device is in the field. Stress testing closes this gap.

Compliance and Stress Testing Answer Different Questions

Compliance testing validates conformance: does this device interoperate correctly within the ecosystem and meet specification-defined electrical parameters? It is a structured, reproducible exercise designed to produce consistent results under consistent conditions, which is both its value and its limitation.

Stress testing asks a different question: how much margin is there, and what happens when real operating conditions begin to consume it? Two examples of potential failure modes illustrate why this distinction matters.

First: If an implementer has a compliant design with only a modest margin at room temperature and nominal supply can consume that margin once the junction temperature rises under sustained load. It is possible to pass compliance under nominal conditions, but fail in real-world scenarios.

Second: A hypothetical device that recovers cleanly from a single L1 exit during compliance testing can still accumulate intermittent CRC errors after repeated power-state cycling. This is the kind of constant ramp-up and ramp-down behavior real inference workloads impose on deployed systems.

These scenarios are not edge cases but are normal operating cases. Compliance testing is not intended to catch them. That is where stress testing comes in. Compliance testing is necessary, but not sufficient.

What Real Stress Testing Actually Covers

Stress testing is a validation philosophy. At the device level, it means characterizing behavior beyond the compliance test points. These include receiver jitter tolerance swept across degraded input conditions, transmitter output across supply and temperature corners, and device-level qualification tests such as ESD, latch-up, and HTOL—the last of which specifically validates that parametric performance doesn't drift under sustained thermal stress over the product's lifetime.

At the system level, the scope expands to encompass the operating conditions encountered in real deployments. Lane-width variation matters because crosstalk and skew behavior differ across x1, x4, and x8 configurations in ways that single-lane compliance won't expose. Speed negotiation testing, which entails exercising fallback and upgrade transitions between PCIe generations under realistic channel and loading conditions, validates LTSSM behavior where it's most likely to develop intermittent issues. Cold and warm boot cycling, across hundreds to thousands of iterations, approximates long-field initialization behavior far more closely than a one-shot compliance bring-up sequence.

Long-duration BER testing deserves particular attention. A link that shows zero errors over a short compliance measurement window can still have a non-zero BER floor that becomes statistically significant over months of continuous operation. Characterizing that floor across different channels and with intentionally degraded signal conditions is the only way to know whether the design has real margin or just hasn't been stressed long enough.

Many of these conditions extend beyond the baseline scope of PCIe compliance validation. To address that gap, Cadence developed additional internal stress-testing methods that evaluate PCIe IP under broader electrical, functional, and system-level conditions. These methods build on standard compliance and qualification practices, extending them into more realistic operating scenarios to improve confidence in field reliability.

Figure 1. Cadence generic multi-lane PCIe validation test setup

Edge AI Makes the Problem Real

Take a concrete deployment: industrial edge AI servers built on PCIe 4.0 platforms. These systems, used in factory automation, logistics, and machine vision, run continuously in thermally variable enclosures, handle sustained multi-sensor inference loads, and operate with little to no local maintenance support. Operating ranges of -20°C to 60°C are standard in these environments. Power-state transitions occur constantly as the NPU idles between inference requests and wakes under load. The PCIe links connecting accelerators, NVMe storage, and high-speed I/O are doing real work in conditions that compliance testing wasn’t designed to replicate.

When a PCIe link develops problems in a data center, the issue is typically visible and diagnosable. Errors are logged, and telemetry is available. Performance degradation can be correlated with system events, and remediation can often be planned without immediate physical access due to redundancy and centralized monitoring.

In a distributed edge deployment, the failure mode is rarely that cooperative. Symptoms tend to be intermittent and might include unexpected inference latency, throughput variance that defies easy explanation, and sporadic link recovery events that don't trigger hard faults but gradually degrade system behavior over time. The root cause is hard to reproduce remotely, and the fix requires physical access to hardware that may be geographically scattered across hundreds or thousands of sites.

The cost of a thin‑margin implementation with limited electrical and timing headroom under real operating conditions can scale quickly with deployment volume, diagnostic effort, and time‑to‑resolution in edge AI environments.

From Compliance to Field Reliability

Compliance is only part of the story. It tells you whether a design meets the standard under controlled conditions. Stress testing goes further, showing how much operating margin remains once thermal cycling, power-state transitions, extended uptime, workload bursts, and channel variation begin to consume it.

For edge AI, where operating environments are harsher and field lifetimes are longer, that difference directly impacts link stability, diagnosability, and long‑term system reliability. This isn’t an abstract quality metric. It determines whether systems behave predictably over years of deployment or slowly degrade in ways that are difficult and costly to diagnose.

Cadence validates PCIe IP across generations with stress testing built into the process. Compliance is only a baseline, while margin characterization is the proof of field readiness.

Learn more about Cadence PCIe IP Solutions for building field‑ready edge AI systems.

Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026

HW202512191014 — Tue, 12 May 2026 04:14:00 GMT

The accelerated growth in data processing and storage demands across HPC data centers and AI factories is expediting PCIe innovation as PCIe links form a foundational fabric for xPU and storage connectivity. While PCIe 6.x is now being deployed in AI...(read more)

Securing Scale-Up AI: Cadence’s Complete UALink Solution

YanTaro C — Tue, 12 May 2026 00:34:00 GMT

As AI systems continue to scale, adding more compute is no longer the biggest challenge. Moving enormous volumes of data between accelerators quickly, predictably, and securely is where the real complexity lies.

Scale-up interconnects have become the backbone of modern AI architectures. They must deliver ultra-low latency, massive bandwidth, and seamless interoperability—while also protecting highly sensitive data in motion. Meeting all these requirements simultaneously is not trivial. This is precisely the challenge that UALink^™ and its integrated security capabilities are designed to solve.

As an early contributor to the UALink ecosystem, Cadence delivers a production-ready solution built for real-world AI deployments. By combining high-performance connectivity IP with integrated security, Cadence enables customers to scale AI infrastructure with confidence.

A Complete Scale-Up Platform

Cadence's UALink IP is more than a collection of individual components—it is a cohesive, end-to-end platform designed to address the full scale-up challenge.

At its core is a UALink controller implementing the complete protocol stack, paired with silicon-proven high-speed PHYs optimized for both short- and long-reach deployments. Around this foundation, Cadence provides subsystem-level integration, including debug, test, and verification capabilities that accelerate bring-up and reduce design risk.

The architecture is designed to scale efficiently. Support for high lane counts and flexible configurations enables system designers to adapt to evolving topologies without redesigning the interconnect. The result is a solution that simplifies integration, shortens time to silicon, and delivers the low-latency, high-bandwidth performance required for next-generation AI accelerators and XPU-to-XPU connectivity.

The Cadence UALink Controller IP implements the full set of spec-derived protocol features required for low-latency, large-scale accelerator fabrics. It supports native UALink read, write, atomic, and message transactions, enabling the load/store semantics and synchronization primitives that modern AI training and inference workloads depend on. Flexible lane bifurcation (1×4, 2×2, 4×1) and support for 212.5Gb/s and 106.25Gb/s serial rates allow system designers to tailor bandwidth, port count, and topology without redesigning the controller. Built-in credit-based flow control (CBFC) and link-level retry (LLR) mechanisms provide deterministic forward progress and resiliency under congestion or transient errors—critical for tightly coupled multi-accelerator execution. Advanced PHY-aware capabilities such as programmable FEC interleaving, error indication bypass, and transmitter pacing further reduce latency and power while sustaining high link utilization, addressing a core UALink objective: maximizing effective bandwidth with predictable, low-jitter behavior at scale.

Why Security Has to Be Built In

As scale-up fabrics become central to AI systems, they also become a critical attack surface. Data exchanged between accelerators—including model weights, intermediate results, and proprietary algorithms—is simply too valuable to leave unprotected. In this context, security cannot be treated as an add-on—it must be designed into the fabric from the start.

Cadence addresses this requirement by integrating UALinkSec, developed by Secure-IC—a Cadence company and the security excellence center of Cadence—directly into the UALink subsystem. Fully aligned with UALink 1.0 security requirements, UALinkSec provides a native security layer for intra-data-center communications.

Security is implemented as a first-class, line rate capability within the Cadence UALink Controller, aligned with UALink v1.0 security requirements. The controller supports AES-GCM with 256-bit keys, perXPUpair master key contexts, and FSM-controlled key derivation and handshake mechanisms, ensuring authenticated, encrypted data movement between accelerators without exposing application software to security complexity. The design sustains full UALink bandwidth through the security layer, supports transparent operation, and allows selective UALlinkSec bypass when applicable—preserving architectural flexibility. Scalable context support for 8 to 1024 accelerators and split crypto cores enables secure operation across large pods while minimizing power overhead when traffic is low. These capabilities directly address the reality that scaleup fabrics now carry highly valuable assets—model parameters, intermediate activations, and proprietary algorithms—making pervasive, low-latency data-in-motion protection essential for production AI deployments.

Built on a high-performance, silicon-optimized, and modular AES-GCM engine derived from the Securyzr^™ neo Core platform, UALinkSec enables encryption, authentication, and integrity protection at line rate. This ensures that security is enforced without introducing latency or compromising bandwidth—preserving the deterministic performance required by AI fabrics.

Scaling AI Securely with Cadence and Secure-IC

As Cadence's security excellence center, Secure-IC brings deep expertise in embedded and hardware-based security, leveraging Securyzr portfolio technologies designed to resist both logical and physical attacks. When combined with Cadence's UALink IP, that expertise becomes a native part of the scale-up fabric.

Together, the solution enables secure data authentication and integrity protection optimized for high-performance AI fabrics, leveraging a high-performance AES-GCM engine and integrated Root-of-Trust-based key management via Securyzr iSE S800 for a secure key lifecycle. Rather than treating security as a separate layer, connectivity, performance, and protection are designed to work together as a unified system.

For system architects, this approach has a very practical benefit: security is addressed early in the design process, reducing late-stage design risk, simplifying compliance, and ensuring robust protection for hyperscale and enterprise AI deployments.

Reducing Complexity, Accelerating Deployment

UALinkSec is available as an optional component within the Cadence UALink subsystem, enabling straightforward adoption without requiring additional integration effort. This tight integration between connectivity and security eliminates the need to stitch together separate IP blocks, ensuring consistent performance, interoperability, and compliance.

For system designers, this translates into less integration effort, faster bring-up through built-in debug and visibility, and confidence that security and performance remain aligned as AI systems scale. As architectures grow in size and complexity, this level of integration and simplicity becomes a clear competitive advantage.

A Foundation for What Comes Next

The next generation of AI systems will be defined not just by how much compute they deploy, but by how efficiently and securely data moves across accelerators. By combining high-performance UALink connectivity IP with Secure-IC's UALinkSec hardware security IP and integrated RoT key management, Cadence delivers a solution that addresses the full set of requirements facing modern AI architectures.

The result is a secure, scalable, standards-based foundation for AI acceleration—built to support today's workloads and ready for what comes next.

Learn more about Secure-IC's UALinkSec ENGINE.

PCIe 7.0 for AI Factories: Why Bandwidth Alone Isn’t Enough

Vanessa Do — Wed, 06 May 2026 19:55:00 GMT

AI factories are scaling rapidly. Training large models and delivering low‑latency inference now requires thousands of GPUs, accelerators, memory devices, and I/O endpoints. System efficiency increasingly depends on how data moves across the infrastructure, not compute power alone.

PCI Express^® (PCIe^®) has long been the interconnect standard for scale‑up systems, connecting CPUs, GPUs, NICs, and memory within the node. By doubling link speed to 128GT/s, PCIe 7.0 delivers up to 512 GB/s of bidirectional bandwidth per x16 link.

Traditional PCIe ordering models were designed for less complex systems, often forcing unrelated traffic to serialize. Even Relaxed Ordering and ID‑based Ordering retain fabric‑enforced constraints that introduce inefficiencies and limit concurrency.

PCIe 7.0 targets next‑generation, highly parallel workloads, including AI training and inference, which generate numerous concurrent and independent transactions. However, ordering itself must evolve to fully utilize PCIe 7.0's increased bandwidth and optimize these AI systems.

Unordered I/O (UIO) allows devices to determine when ordering is unnecessary. Rather than relying on the fabric to enforce sequencing, UIO shifts responsibility to the endpoints. This enables higher parallelism, lower latency, and better sustained utilization of PCIe links for AI workloads.

With the evolution of data centers into AI factories, interconnect design has become as critical as compute and memory—across both scale‑up architectures within the node and scale‑out fabrics connecting accelerators and memory across systems. In this environment, PCIe serves as the foundational backbone for control and data movement, orchestrating connectivity, ordering, and efficiency across the entire interconnect hierarchy.

Cadence's PHY and controller IP for PCIe 7.0 are designed to support these complex architectures underlying today's AI infrastructure, enabling high‑bandwidth, low‑latency data movement while accommodating advanced ordering models like UIO.

To learn why bandwidth alone is no longer sufficient and how PCIe ordering is evolving to maximize system efficiency, read the PCIe 7.0 fundamentals mini-series on EDN:

👉 PCIe 7.0 fundamentals: Baseline ordering rules

👉 PCIe 7.0: Addressing legacy ordering limitations with UIO

🔗 Learn more about Cadence PCIe and CXL IP

SOCAMM: Modernizing Data Center Memory with LPDDR6/5X

Frank Ferro — Thu, 09 Apr 2026 00:30:00 GMT

Small Outline Compression-Attached Memory Module (SOCAMM) has made its way into the data center as an alternative to external CPU memory, due to its high performance, low power, memory capacity, and scalability. The latest CPUs used in AI factories r...(read more)

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

Joe C — Fri, 03 Apr 2026 20:30:00 GMT

From smart cameras to autonomous vehicles and compact edge servers, edge AI is pushing more compute, storage, and connectivity into smaller, more power-constrained systems deployed outside the data center. These designs must simultaneously ingest sensor data, move information to local accelerators, connect to displays or storage, and maintain reliable network links—all within tight area, thermal, and BOM limits. As a result, system designers face a fundamental tradeoff: supporting more interfaces typically means integrating more PHY IP, each consuming valuable die area, power, and board space that edge platforms can least afford.

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

For edge AI, this translates directly into smaller die area, simplified routing, lower BOM cost (including fewer IP licenses, discrete components, and board connectors), and reduced system-level power. This combination is proving increasingly essential as edge devices are tasked with performing more local inference while maintaining energy efficiency.

Where It Matters Most

The benefits of flexible and simultaneous multi-protocol operation are evident in the most demanding edge environments:

Smart Gateways

USB connects sensors or Wi-Fi/Bluetooth modules, while PCIe links to AI accelerators or SSDs. Cadence's multi-protocol PHY eliminates redundant IP blocks, reducing both die area and BOM cost.

Machine Vision Systems

DisplayPort drives high-resolution monitors while PCIe moves data to compute engines. A single Cadence multi-protocol PHY handles both without additional discrete components.

Automotive Edge Compute

Ethernet provides in-vehicle networking, while PCIe feeds AI processors for ADAS and autonomy. Cadence's multi-protocol PHY is capable of supporting AEC Q100 standards, making it suitable for these safety-critical environments.

Built to Scale Across Your Product Line

Because the same PHY architecture works across product lines, design teams avoid redesigning boards for every new product variant. One validated block can be reused across gateway, machine vision, and automotive SKUs, reducing both qualification time and time-to-market.

Reusing a validated PHY architecture also reduces verification effort and integration risk, which is especially critical in long-lifecycle and safety-conscious edge deployments.

Cadence demonstrated the PHY's multi-protocol support on a live silicon test chip and captured it on video. Watch the demo to see how the engineering team approaches multi-protocol flexibility across smart gateway, machine vision, and automotive designs.

To learn more about Cadence's multi-protocol PHY solutions for edge AI designs, visit cadence.com.

Understanding the Difference Between a Monolithic SoC and a Chiplet

Mick Posner — Thu, 19 Mar 2026 12:00:00 GMT

I am often asked, "What is the difference between a traditional SoC die and a chiplet die?" At a high level, the answer is that a traditional SoC is designed as a standalone single-die packaged chip, while a chiplet is part of a larger system of multiple dies packaged together. This simple answer inevitably leads to a more involved answer. To facilitate a system of chiplets, each chiplet must understand how to manage itself within the system. One common misconception is that adding a die-to-die interface to a design equals a "chiplet." While that is part of the chiplet function, it is nowhere near solving all the associated challenges.

To operate as a chiplet, a design must first address a number of considerations. These include how it boots (secure or insecure?), how it's debugged (standalone or across chiplets?), how common resources (such as memory) are managed, how clocking and resets are distributed, how it communicates with other chiplets, and, for designs where safety is crucial, how faults are captured. Finally, all these capabilities should be designed to a common specification, such as the new Foundational Chiplet System Architecture (FCSA), being developed as part of the Open Chiplet Economy (OCE), to ensure multi-chiplet interoperability. The FCSA specification defines common interfaces and protocols between different types of chiplets.

Figure 1. Common Chiplet Interfaces

The Cadence Chiplet Framework

The good news for chiplet designers is that Cadence has been pondering the problems of multi-die chiplet integration and interoperability, and the need for specific chiplet management capabilities, for a couple of years now, and has developed a solution. The Cadence Chiplet Framework is a comprehensive hardware and software solution designed to make this transition seamless. The Cadence Chiplet Framework accelerates chiplet development and ensures cross-chiplet interoperability by standardizing common interfaces.

The Cadence Chiplet Framework provides a pre-verified and integrated set of subsystems that manage everything from boot-up and security to die-to-die communication. It acts as the foundational blueprint for creating complex multi-chiplet systems. Let's explore the key subsystems that compose this powerful framework and understand how each component contributes to a successful chiplet-based design.

Figure 2. Cadence Chiplet Framework

CSCP Subsystem

The system and security control processor (CSCP) subsystem is at the heart of the Cadence Chiplet Framework. This critical component acts as the central control system for each chiplet, and every chiplet in the system should include, at a minimum, one CSCP. It is responsible for orchestrating the boot process, managing system-level functions, and ensuring robust security within and across chiplets.

Figure 3. CSCP subsystem

The CSCP includes an efficient and lower-power control processor, which executes dedicated firmware. One of its primary roles is to manage the chiplet boot flow, ensuring that each die powers up correctly and in the proper sequence. It initializes essential components like interconnects, memory controllers, and the UCIe^™ interface, setting the stage for communication between chiplets. For security, the CSCP interfaces with a built-in root of trust (RoT), the Cadence Securyzr solution, which handles secure boot, attestation, and lifecycle management, establishing a secure foundation for the system's operation.

Figure 4. Cadence Securyzr, the secure root of trust solution

Key functions of the CSCP firmware include:

System-level control: Distributes clock and power control across all chiplets.
Communication: Establishes communication pathways between chiplets and supports the system control and management interface (SCMI) for interaction with other components.
Security and recovery: Provides mechanisms for secure execution, secure firmware upgrades, and device recovery, crucial for maintaining device integrity in the field.

Figure 5. CSCP firmware

DBG Subsystem

Complex systems require robust debugging capabilities, and multi-chiplet designs are no exception. The debug (DBG) subsystem is housed in an always-on power domain, providing standalone debugging capabilities that are independent of the main system's operational state.

This is particularly important during development and when diagnosing issues in the field. The DBG facilitates debug communication between chiplets and allows an external debugger to be used even when the primary die-to-die interface (UCIe Mainband) is not active. It also supports a debug cross-trigger interface, enabling engineers to synchronize debug events across different chiplets for more effective system-wide analysis.

Figure 6. DBG subsystem

CON Subsystem

While the CSCP manages the overall system, local control within each subsystem is handled by dedicated control (CON) subsystems. These configurable blocks are implemented throughout the design, providing granular control over local functions.

Each CON includes a local controller for power, clock, and resets. It communicates with the central SCP to ensure its operations are synchronized with the rest of the system. Additionally, the CON features generic control and status registers (CSRs) that are used to configure IP interfaces and manage miscellaneous functions. For advanced designs, a CON can also integrate optional components like local phase-locked loops (PLLs) for clock generation, on-die sensors for monitoring, and a fault management unit (FMU) for detecting local errors.

Figure 7. CON Subsystem

NoC Subsystem

Modern designs require efficiently moving vast amounts of data between different functional blocks. The network-on-chip (NoC) subsystem serves as the data highway both within and between subsystems. It provides a high-performance data network that connects various components, such as processors, memory, and I/Os.

The framework is flexible, offering the choice of non-coherent and coherent networks, including a mix of each, catering to a wide range of application needs. To manage memory access, the NoC subsystem supports an optional I/O memory management unit (IO-MMU) to translate virtual addresses to physical addresses, along with an address translation cache to speed up this process.

Die-to-Die Interface (UCIe) Subsystem

The core of a chiplet-based design lies in its ability to connect multiple dies so they function as a single, cohesive system. The die-to-die interface subsystem makes this possible using the UCIe IP from Cadence. This configurable subsystem includes the necessary controllers and PHYs to establish a reliable, high-bandwidth link between chiplets.

The die-to-die subsystem supports a variety of industry standards, including the AMBA CHI-C2C, ACE-lite + DVM C2C, and AXI C2C protocols, ensuring interoperability. A critical function of this subsystem is managing interrupts across chiplets. It includes an interrupt encoder and decoder that can translate MSI messages, allowing a core on one chiplet to efficiently signal an interrupt to a core on another.

Figure 8. Cadence UCIe subsystem

Optional CSMP Subsystem

For applications that require functional safety, such as automotive or industrial systems, the framework offers an optional safety management processor (CSMP) subsystem. This processor with a firmware-driven subsystem is dedicated to monitoring the health of the entire system and managing fault collection and action-taking.

Figure 9. SMP subsystem

The CSMP subsystem works in conjunction with the FMUs distributed across the chip. Its firmware performs system-level distributed fault monitoring and can aggregate error reports from all chiplets.

Key responsibilities of the CSMP firmware include:

Power-On Self-Test (POST): Establishes an acceptable initial safety state upon boot.
Error handling: Determines the system's safety state based on events from all FMUs and coordinates system-wide error handling based on fault type and severity.
Recovery and notification: Can trigger recovery actions, communicate with the SCP to reset IP, or notify high-level software of faults.
Logging: Captures all faults in system logs for diagnostics and compliance.

Benefits of the Cadence Chiplet Framework

By providing a pre-integrated and verified set of hardware and software subsystems, the Cadence Chiplet Framework offers significant advantages for companies developing next-generation chiplet-based systems.

Modularity and flexibility: The framework allows designers to focus on their unique value-add, knowing that the foundational chiplet control, security, and communication infrastructure is already in place.
Reduced time to market: By starting with a proven chiplet management foundation, design teams can dramatically shorten development cycles and reduce verification effort.
Enhanced efficiency: The integrated chiplet framework approach addresses key challenges in multi-chiplet design, such as system-level power management, security, and debug, resulting in a more efficient and robust final product.
Interoperability: Based on mature, open, chiplet system architecture specifications, the framework ensures interoperability across chiplet designs.

The Cadence Chiplet Framework provides the essential building blocks for navigating the complexities of multi-die chiplet integration. It empowers engineers to harness the full potential of chiplet-based design, paving the way for a new era of semiconductor innovation.

Resources

Download our eBook, Cadence Chiplet Solutions: Helping You Realize Your Chiplet Ambitions
Watch our webinar: Cadence Chiplet Solutions: Helping You Realize Your Chiplet Ambitions
Read our news release: Cadence Launches Partner Ecosystem to Accelerate Chiplet Time to Market
Blog: From Spec to Silicon: Successful Physical AI System Chiplet Bring-Up

Learn more about the Cadence Chiplet solutions.

Transforming the Automotive Experience with Cadence Tensilica DSPs

SriramK — Fri, 06 Mar 2026 04:54:00 GMT

Experience Innovation at Embedded World 2026

The automotive industry has shifted its focus from traditional performance metrics to prioritizing safety and comfort. As vehicles evolve into software-defined environments, the interior cabin is emerging as a sanctuary—offering enhanced safety, superior comfort, and immersive high-fidelity entertainment for all occupants. At this year's embedded world, Cadence is proud to showcase how Tensilica DSPs are at the forefront of this transformation. In collaboration with leading ecosystem partners, Cadence will present a series of engaging demonstrations that highlight the latest in-cabin technology advancements.

Featured Demonstrations

The "quiet bubble" Active Noise Cancellation with Silentium: Road noise can significantly detract from a premium cabin experience. To address this, Cadence has partnered with Silentium to demonstrate their Quiet Bubble™ software running on Tensilica HiFi DSPs. Leveraging low-latency processing, this system actively cancels unwanted road and tire noise in real time, delivering a serene and whisper-quiet interior. Passengers can enjoy clear conversations and a more focused driving experience, free from external distractions.
In-cabin sensing and occupant monitoring on NXP RT700 platform: Tensilica DSPs are instrumental in enhancing the safety of drivers and passengers. This demonstration running on the NXP RT700 platform highlights advanced in-cabin sensing capabilities and workloads processed on our HiFi 1 DSP core, including driver distraction detection, real-time monitoring of vital signs, and child presence detection to ensure no child or pet is inadvertently left behind. The importance of these technologies has grown as the Euro NCAP 2026 protocols now demand higher safety standards. Achieving a 5-star safety rating requires manufacturers to implement not only alert systems but also direct-sensing and active-intervention solutions.
Long-range radar chipset from NXP S32R47: Targeting L2+ to L4 automotive ADAS applications, Cadence Tensilica FloatingPoint DSPs and FFT accelerators provide just the right solution under the hood to process radar-dense point clouds, perform object detection, classify and separate tightly spaced objects, sense debris next to these objects, and detect vulnerable road users (VRUs), enabling safer highway and urban driving. Cadence DSPs also support multimodal sensing and lidar sensor processing.

Whether your interests lie in active acoustics, AI-driven safety features, or the future of zonal vehicle architecture, Cadence experts will be available to provide in-depth explanations and demonstrations of the latest technology.

Where: Hall 4, Booth 219
When: March 10-12, 2026

For more information, visit Summary - embedded world 2026 and contact us to request a meeting.

Accelerating Chiplet Innovation with a New Partner Ecosystem

Mick Posner — Wed, 04 Mar 2026 16:57:00 GMT

The semiconductor industry is currently undergoing a massive shift. As we push the boundaries of performance in physical AI, data centers, and high-performance computing (HPC), traditional monolithic chip design is hitting physical and economic walls. The answer for many engineers and architects is chiplets, a modular approach that enables the mixing and matching of silicon dies to create powerful, highly customized systems.

However, transitioning from a single-die SoC (system on chip) to a multi-die SiP (system in package) brings a surge in engineering complexity. How do you ensure different pieces of silicon from different vendors communicate with each other correctly?

To tackle these challenges head-on, Cadence has announced a major leap forward: a Chiplet Spec-to-Packaged Parts ecosystem. This initiative is designed to streamline the engineering process and accelerate time to market. Through our partnerships, Cadence is paving a lower-risk path for the next generation of chiplet adoption.

The Spec-to-Packaged Parts Vision

The core of this announcement is the Cadence Physical AI chiplet platform. This isn't just a set of tools. It's a comprehensive configurable platform designed to bridge the gap between a chiplet specification and a final, known-good die (KGD) or packaged (multiple dies) part.

Cadence has built spec-driven automation that generates chiplet framework architectures. These frameworks combine Cadence's own IP with third-party partner IP, all wrapped in critical chiplet management services, as well as built-in security and safety features.

The goal is clear: Accelerate the spec-to-parts process while reducing risk!

Developing chiplets often feels like venturing into uncharted territory. By providing a pre-verified platform, Cadence enables design teams to start with a robust foundation rather than building everything from scratch. In addition to significantly reducing customer-specific chiplet development time, this approach optimizes costs, provides the flexibility needed for customization, and enables configurability that modern applications demand.

Figure 1. Cadence Physical AI Chiplet Platform

Critically, the generated chiplet architectures are standards-compliant. They adhere to the Arm Chiplet System Architecture and the future OCP Foundational Chiplet System Architecture, ensuring broad interoperability. The Cadence Chiplet Framework encapsulates these capabilities, which are reusable across chiplets, accelerating chiplet development and ensuring cross-chiplet interoperability through standardization.

Figure 2. Cadence Chiplet Framework

Strategic Partners: Arm and Samsung

Two key collaborations anchor this new ecosystem, signaling the industry-wide support for this initiative.

Arm: Powering Physical AI

Building on a long history of collaboration, Cadence and Arm have forged a new strategic partnership focused on physical AI.

This agreement grants Cadence access to the advanced Arm Zena Compute Subsystem (CSS). This is a game-changer for edge AI processing requirements in automobiles, robotics, and drones. By integrating Arm's technology, the platform empowers safer, smarter, and more efficient systems.

Samsung Foundry: Future Prototype Silicon Proof

One of the biggest hurdles in chiplet adoption is proving real-world functionality. To showcase Cadence's chiplet expertise and Samsung's semiconductor technology, Cadence is partnering with Samsung Foundry to build a real-world silicon prototype of the Physical AI Chiplet Platform. Using Samsung's SF5A process for automotive, the prototype will feature an Arm Zena CSS-based chiplet, a central system chiplet, and an AI chiplet powered by Cadence Neo NPUs.

A Robust IP Partner and Silicon Analytics Ecosystem

An ecosystem is defined by the strength of its community. Beyond Samsung and Arm, Cadence has enlisted a diverse group of initial IP partners and a silicon analytics company to ensure important aspects of chiplet designs for Physical AI are covered.

Arteris: Providing physically-aware network-on-chip (NoC) IP products like Ncore for coherent systems and FlexGen for non-coherent ones to handle high bandwidth, low latency, and power-efficient interconnects in multi-die systems.

eMemory: Contributing enhanced one-time programmable (OTP) memory that complements Cadence's security subsystems, ensuring secure storage and key management.

M31 Technology: Delivering MIPI PHY interface IP, essential for automotive and high-volume consumer applications requiring flexible camera and display integration.

proteanTecs: Embedding a hardware health and performance monitoring system for telemetry and silicon analytics SW, per chiplet die and across chiplet types, to enable power-efficient, safe, and reliable performance of next-gen systems.

Silicon Creations: Providing ultra-fast, multiphase PLL clocking solutions optimized for the Cadence Chiplet Framework, UCIe die-to-die IP, and interface IP.

Trilinear Technologies: Delivering advanced DisplayPort IP to drive high-performance video connectivity.

Conclusion

As David Glasco, vice president of the Compute Solutions Group at Cadence, noted in our recent announcement, this ecosystem represents a "significant milestone in chiplet enablement."

In an era of skyrocketing design complexity, achieving the necessary performance and cost efficiency demands collaboration and standardization. By combining extensive internal expertise with a powerful network of partners like Arm and Samsung Foundry and specialized IP and silicon analytics providers, Cadence is building a launchpad for the next generation of physical AI and HPC innovations.

For engineers and architects, this means less time wrestling with integration headaches and more time focusing on differentiation and innovation.

Resources

Read the news release: Cadence Launches Partner Ecosystem to Accelerate Chiplet Time to Market
Watch our webinar: Cadence Chiplet Solutions: Helping You Realize Your Chiplet Ambitions.
Learn more: Cadence Chiplet Solutions

The Memory Imperative for Next-Generation AI Accelerator SoCs

Subash Peddu — Wed, 18 Feb 2026 04:30:00 GMT

The tremendous growth in large language model (LLM) size corresponds with an equally dramatic rise in agentic AI applications, which are being adopted rapidly across both enterprise and consumer markets. To accommodate this demand, hyperscale providers are deploying next-generation data centers at an unprecedented rate and scale. Each of these data centers hosts millions of AI accelerators to run agentic AI workloads. One notable example is Meta’s Hyperion data center, which is projected to consume up to 5GW of compute power in a footprint that would cover a significant portion of Manhattan.

AI accelerators are key components of the AI data center tasked with speeding up the complex mathematical calculations required for AI and machine learning (ML). As the demand for AI continues to skyrocket, it’s crucial that SoCs provide the necessary “brain power” for these AI accelerators to keep pace. In this dynamic environment, SoC architects must carefully balance multiple factors to optimize their next-generation designs. When faced with the task of defining SoCs for tomorrow’s AI accelerators, four key criteria warrant close consideration: performance, power efficiency, SoC layout optimization, and futureproofing.

Performance

Next-generation LLMs, which can reach up to 100-trillion-parameter scale and beyond, demand exceptional computational throughput. While compute subsystems are advancing at an estimated 20X every two years, memory subsystems are improving only 2–3X over three years, creating what the industry now calls the memory wall.
In the face of this challenge, high-bandwidth memory (HBM) remains the preferred solution with its wide I/O architecture and superior performance. The latest HBM standard, HBM4, doubles the number of data lines from 1,024 to 2,048 compared to the previous generation (HBM3). This enables a significant increase in memory bandwidth (2X just due to doubling the data bits), unlocking higher overall AI accelerator performance.

Another key performance metric is memory data rate. The HBM4 standard increases the per-bit data rate to 8Gbps, from 6.4Gbps in HBM3. However, DRAM vendors are quickly moving beyond this speed due to the ever-increasing performance requirements of AI accelerators. To achieve these speeds, SoC developers require a memory subsystem, including a memory controller and physical layer (PHY), that can perform at or beyond the DRAM speed to ensure adequate system margin and high reliability. For example, in April 2025, Cadence announced an HBM4 PHY and controller that perform at 12.8Gbps, or 3.3TB/s of memory bandwidth, per HBM4 DRAM device. At this speed, AI hardware developers will have 4X the memory bandwidth available per DRAM when compared to the previous generation! The industry is not stopping, so expect to see even higher speeds to support AI’s insatiable demand for memory bandwidth.

Power Efficiency

Electricity is a major operational cost for modern data centers. In addition to powering SoCs and racks, data center operators must account for substantial cooling infrastructure and the power required to run it. With future AI/ML workloads measured in terabytes/s, power-efficient data transfers are even more critical for managing cost and improving sustainability.

For memory subsystems, efficient data movement between the SoC and HBM plays a critical role in overall power consumption. Measured in picojoules per bit (pJ/bit), lower energy-per-bit transfer directly enables higher energy efficiency, reduced cooling requirements, and lower total cost of ownership (TCO). By minimizing pJ/bit at the HBM PHY, systems achieve meaningful power savings that support sustainability goals while improving operational economics.

SoC Layout Optimization

In modern AI-centric SoCs, the core area is the most valuable real estate. Achieving higher AI performance depends on maximizing the silicon allocated to core logic—where the AI compute subsystem resides—while minimizing the footprint of the memory subsystem, which must still deliver massive bandwidth. As a result, both the SoC core area and shoreline must be extremely efficient to achieve peak performance.

Today’s AI SoCs are frequently designed at or near the reticle limit. At this scale, die edges must fit as many HBM4 PHYs as possible to maximize memory bandwidth per SoC while minimizing impact on compute core die area. Figure 1 illustrates an AI SoC layout with the HBM4 physical layers utilizing the area on the east and west sides of the die, with the compute core in the center. The long and narrow PHY layout efficiently uses the die edges with minimal waste between PHYs, while preserving valuable core logic space. In this example, the SoC will have 20TB/s memory bandwidth available with a 12.8Gbps memory subsystem.
Optimizing HBM4 PHY dimensions is more than just a packaging concern. It is a fundamental design decision that directly impacts AI performance, scalability, and silicon efficiency.

Figure 1: Example SoC layout optimized for maximum bandwidth

Futureproofing

With SoC design and fabrication cycles spanning 12 to 24 months, products designed today must anticipate the availability of faster DRAM devices at the time of system deployment. This means that SoC designs should incorporate HBM4 PHY and controller technology capable of supporting the highest speed grades today while being able to scale seamlessly as future DRAM generations become available.

At Cadence, we specialize in tackling these detailed design challenges. We are ready to provide the necessary technical information and support to quickly start your next-generation memory subsystem design. To see our industry-leading HBM IP in action, visit us at Booth 300 at the 2026 Chiplet Summit, where we’ll be demonstrating our 3nm HBM3E PHY operating at 14.4Gbps.

Learn more about Cadence’s HBM4 PHY and Controller IP.

Accelerating Chiplet Interoperability

Mick Posner — Mon, 16 Feb 2026 13:00:00 GMT

In the chiplet marketplace, the vision of a library of chiplets that can be mixed and matched requires interoperability between chiplets (sometimes from different sources), meaning standardization is essential. By establishing common chiplet system standards, designers will be able to seamlessly integrate chiplets from different vendors, reducing development time and costs while continuing to drive innovation. Interoperability ensures that diverse components work together reliably, unlocking new possibilities for modular system design and expanding the market for all participants.

While there are several specifications that aim to define chiplet systems, the Arm^® Chiplet System Architecture (Arm CSA) is by far the most comprehensive and mature. Arm recently contributed the Arm CSA to the Open Compute Project (OCP) to form the Foundational Chiplet System Architecture (FCSA). FCSA will deliver a vendor and CPU-neutral architecture, common system partition guidelines, and a shared vocabulary and set of standards for system-level and interface definitions between chiplets, complementing existing interconnect standards like the Universal Chiplet Interconnect Express (UCIe^™).

Think of OCP FCSA as the expansive baseline standard covering broad Chiplet system architecture and Arm CSA as the Arm-specific implementation of OCP FCSA. I know Arm CSA came first, in the future, Arm CSA will follow and build upon the OCP FCSA.

The OCP's FCSA offers several key benefits:

Modularity and Interoperability: It enables modular design at the silicon level, allowing different chiplets to work seamlessly together, regardless of the manufacturer.
Reduced Fragmentation: By providing a neutral, standardized framework, it minimizes industry fragmentation and promotes collaboration across companies.
Open Ecosystem: It encourages innovation by fostering an open chiplet economy, where companies can contribute and benefit from shared advancements.
Scalability: It supports scalable solutions for industries like automotive and computing, where flexible and efficient silicon designs are critical.
Cost Efficiency: It facilitates cost-effective development by reusing standardized components rather than designing custom silicon for every application.
Accelerated Innovation: It speeds up time to market for new technologies by simplifying the integration of diverse chiplets into cohesive systems.

This architecture is a significant step toward a more collaborative and efficient future for chiplet-based designs.

Designed with interoperability in mind, the Cadence Physical AI Chiplet platform and its underlying Cadence Chiplet Framework follow the Arm CSA and are expected to align with the OCP FCSA specification as it matures. The Cadence implementation, in addition, incorporates chiplet system capabilities above and beyond the specification that our engineers deemed essential for physical AI applications and generalized chiplet use cases. Cadence is excited about the evolution of the new Foundation Chiplet System Architecture specification and is committed to driving this standard forward through leadership and future contributions.

Learn more about Cadence Chiplet Solutions.

Cadence Tapes Out 32GT/s UCIe IP Subsystem on Samsung 4nm Technology

MBhatnagar — Wed, 11 Feb 2026 01:30:00 GMT

With the rapidly increasing connectivity demands driven by AI/ML and HPC/datacenter use cases, high-throughput die-to-die connectivity is more essential than ever. Cadence has been at the forefront of die-to-die connectivity solutions since 2018. In keeping with a rapidly broadening portfolio of die-to-die connectivity solutions, Cadence has taped out its IP subsystem for 32GT/s UCIe solution on Samsung's 4nm (SF4X) process technology. Building on eight years of expertise in die-to-die solutions and the success of multiple UCIe IP subsystem test chips, this next-generation product delivers improved performance and flexibility while maintaining the reliability and precision proven by its predecessors.

The 32GT/s UCIe solution builds upon silicon-proven IP at 32GT/s and 16GT/s speeds—the latter forming the first two UCIe transceiver publications—this is peer-reviewed and proven performance. Key features include:

High-Speed Data Transfer Ranging from 4Gbps to 32Gbps: This IP supports all UCIe data transfer rates from 4Gbps to 32Gbps, offering flexibility across various customer applications. This broad speed support makes the IP ideal for diverse use cases, providing scalable performance to meet the requirements of both low-power systems and high-throughput systems.
Optimized Design for 32Gbps Speed and Wide Interoperability: The IP is optimized to operate seamlessly at the UCIe specification speed of 32Gbps, ensuring robust interoperability with any UCIe solution. This optimization enables the best performance metrics and broader interoperability.
Universal Interoperability for Various Transmitter and Receiver Configurations: The UCIe transmitter in Cadence's IP supports both half-rate and quad-rate UCIe receiver implementations, ensuring broad compatibility across various configurations. With the ability to generate clocks up to 16GHz, this IP provides robust support for data rates up to 32Gbps, ensuring full interoperability in diverse UCIe applications.
Self-Calibrating Capabilities and Hardware-Based Bring-Up with No Firmware Requirements: A key feature of Cadence's UCIe solutions is their self-calibration functionality and hardware-based bring-up, which eliminates the need for firmware intervention during system initialization. This significantly simplifies the setup process by removing the need for firmware loading.
At-Rate Loopback for Wafer Sort and Validation: The IP features at-rate loopback at 32Gbps, enabling efficient wafer sort—a key feature for D2D solutions—and simplifying packaged part validation. Additionally, the full die-to-die (D2D) loopback mode ensures comprehensive validation across the entire link, including the channel, from one die to its partner and back, offering complete testing coverage for high-reliability systems.
Integrated Internal PLL: Like all previous Cadence UCIe IP, this IP includes an internal Phase-Locked Loop (PLL) that autonomously generates the necessary Lclk and high-speed clocks within the IP. The user only needs to supply a 100MHz reference clock, with the option to provide the Lclk from the SoC. This allows for simplified clock management, streamlined integration, and reduced system complexity.
Robust Performance Under Extreme Operating Conditions: Cadence's UCIe IP solutions feature a "Maintenance Mode" that performs regular background runtime recalibration to ensure uninterrupted operation, even under changing conditions such as supply voltage and temperature drifts (ranging from -40°C to 125°C), covering the full industrial range.
Support for Vendor-Defined Messaging Over Sideband Links: The IP supports vendor-defined messages over sideband links, fully compliant with UCIe specifications. This feature ensures effective communication and control across the die-to-die interconnect, enhancing system integration. It is included in both the 16Gbps and 32Gbps versions of our UCIe IP solutions.
Broad Protocol Support: Cadence's 32G UCIe IP also offers broad protocol support to enable pre-validated, high-performance, low-latency, and low-power subsystems for any application.

Cadence's tapeout of the 32GT/s IP subsystem marks a major advancement in die-to-die connectivity. It offers high performance, power efficiency, and integration, supporting a range of advanced packaging options. This IP builds on the reliability and precision of Cadence's previously proven Gen2 UCIe-SP and Gen1 UCIe-SP and UCIe-AP solutions, continuing to support features such as self-calibrating capabilities, hardware-based bring-up, and robust performance under varying conditions. As a contributing member of the UCIe consortium, Cadence is helping to shape the future of the chiplet ecosystem and meet the needs of modern high-performance computing, data centers, and AI/ML applications.

For further information or inquiries, please contact us to explore how our UCIe IP can support your projects. Learn more about Cadence's Universal Chiplet Interconnect Express (UCIe) PHY and Controller.

CES 2026 Recap: Trust Built on a Real, Working eUSB2V2 System Demo

DavidShin — Tue, 10 Feb 2026 04:54:00 GMT

Nothing builds trust like a real working system.

That was the guiding principle behind our CES 2026 showcase in Las Vegas—where we successfully demonstrated what we believe is an industry-first 3nm eUSB2V2 PHY IP alongside eUSB2V2 controller IPs (both host and device) running together in a complete, end-to-end system. The result: a live, real-world eUSB2V2 data path performing at speeds of up to 4.8 Gbps, highlighting the promise of this new USB interface protocol.

Why This Demo Mattered

When a new interface technology emerges, specs and simulations are only part of the story. What customers and partners truly need is confidence that the ecosystem can work, in practice, across chips, controllers, PHYs, platforms, and devices.

At CES 2026, we brought that confidence to life with a demo designed to answer a simple question: Can eUSB2V2 deliver real throughput in real conditions—with real system behavior and interoperability?

Our answer: Yes, live, on the show floor.

https://youtu.be/gkZz-8faQBI

Demo Setup: A Complete Device to Host the eUSB2V2 System

The demo system was built to represent a realistic, end-to-end data flow—capturing video on the device side and delivering it reliably to the host side for processing and display.

System architecture (high level):

3nm eUSB2V2 PHY test chips on both host and device sides
Host and device controllers implemented on FPGA boards
PC/ATX boards in the loop to support the full end-to-end pipeline
SMA cable connectivity between device PHY and host PHY to ensure robust signal integrity
Monitor display on the host side showing the live video feed

How Data Flowed

A high-resolution camera streamed maximum raw data in real time through the PC/ATX boards into the FPGA-based system. The device PHY communicated to the host PHY over SMA, and on the host side, the FPGA board ran the host controller, connecting to a PC/ATX board and monitor to display the live captured video.

This seamless flow showcased the efficiency and performance of eUSB2V2 in a practical, real-world scenario—not just a lab bench proof.

The Highlight: Two Simultaneous 4K Video Streams Over eUSB2V2

To push the system beyond a single “happy path” workload, we demonstrated two video sources transferring simultaneously from the eUSB2V2 device side to the eUSB2V2 host side.

1. 4K Live Video (UVC) — Uncompressed YUV

One stream was a 4K live video feed captured from a 4K webcam, transported as uncompressed YUV video from the device side to the host side. On the host, the system SoC performed video enhancement and rendered the output to the monitor.

Protocol/class used: UVC (USB Video Class)
Key takeaway: eUSB2V2 can sustain demanding real-time video movement without relying on compression tricks.

2. 4K Recorded Video (MSC) — Bulk Transfer from SSD

The second stream demonstrated bulk data transfer: a 4K recorded video stored on an SSD acting as the device. The host system received the content and rendered it on the display.

Protocol/class used: MSC (Mass Storage Class)
Key takeaway: eUSB2V2 supports high-throughput bulk workloads alongside real-time streaming.

A Critical Enabler: UTMI v2.0 Bridging Controller and PHY

A key element of the demo was how we connected the system pieces cleanly and correctly.

Controllers (host + device): running on Cadence FPGA platforms
3nm PHY IP: implemented in test chips
Bridge/interface: the newly published UTMI (USB 2.0 Transceiver Macrocell Interface) v2.0

This enabled a smooth connection between the controller IP in FPGA and the PHY IP in silicon—helping validate the full stack of the solution.

What This Proves: eUSB2V2 As a Complete Solution

This CES 2026 demonstration wasn’t just a speed milestone. It was a system-level proof that eUSB2V2 can be delivered as a complete, interoperable solution:

Industry-first 3nm eUSB2V2 PHY IP (host + device PHY coverage)
Host and device controller IPs
A validated, real-time system that shows how the pieces operate together in the field

And importantly, it provides confidence for adoption—especially because it supports seamless interoperability between:

Host-side solutions already licensed by tier-1 customers, and
A variety of device-side solution providers across the ecosystem

Looking Forward: Built for What's Next – Consumer and Edge AI

Beyond consumer connectivity, this milestone reflects a strategic direction toward the anticipated edge AI era—where bandwidth, latency, power efficiency, and reliability become increasingly critical for distributed intelligence and sensor-rich devices.

This is about showing not only what’s possible today—but what can scale into next-generation applications tomorrow.

Conclusion

eUSB2V2 delivers the flexibility modern systems demand, combining high data rates, configurable link options, reduced EMI, and low power operation. As SoCs move to advanced process nodes while connected devices remain on mature nodes, eUSB2V2 is quickly becoming the go-to USB interface to bridge the gap, extending the proven, ubiquitous USB ecosystem.

Cadence, a long-time leader in USB IP, has expanded its portfolio with complete, end-to-end eUSB2V2 solutions, including host and peripheral controllers, PHYs, drivers, and Verification IP. Learn more at cadence.com

Scale-Up and Scale-Out IP for Optical Interconnect for Accelerated Computing

HW202512191014 — Fri, 06 Feb 2026 17:00:00 GMT

Optical connectivity is foundational to modern data centers, enabling high-bandwidth, low-latency data movement across switches, routers, servers, and racks. With the rise of AI factories, its importance has increased dramatically. Optical links prov...(read more)