Tensilica and Design IP Blogs

Remember automobiles from a few years ago? They were pretty simple machines with lots of small microprocessors distributed across the whole vehicle and doing fairly simple tasks. Semiconductors have been in automobiles for several years, of course, with simple 8- and 16-bit microcontrollers performing functions like Anti-lock Braking (ABS). But today’s automobiles are a different beast. They incorporate several compute...

You might have seen the graph below about the increase in monthly internet traffic around the world. Ever wondered what was causing it? If you think all that traffic is simply due to people binge-watching House of Cards on Netflix, or uploading the...

With cloud technology going vertical, everything is changing. The world is connected like never before—managing and processing large amount of data, every single second. Augmented/Virtual Reality is the latest game changer, even in its early stage of development and proliferation. The gathering of semiconductor experts at CDNLive Israel confirmed these and other trends are impacting everything from IP to tools to business...

Memcon is an event like few others, where SoC architects congregate to learn and debate the strategies of system design to keep up with the insatiable data/throughput demands of today’s electronics. The topics range from memory technology to system architectures, as captured in the MemCon 2015 Proceedings . While this year’s agenda will provide similar, updated information, there are 3 things you probably don’t know...

Microsoft provided details of their HoloLens HPU at HotChips this week, revealing the use of 24 optimized Tensilica processors to speed up all the sensor processing by up to 200x. The media has taken notice as well with reports appearing across all of the popular sites. What Microsoft did sounds pretty extreme; creating a processor to make it run their algorithms in fewer cycles so as to keep both the performance...

MIPI DevCon 2016 – Mobile and Beyond The word “beyond” may bring up thoughts of the new Star Trek Beyond movie, or for those of you who are fascinated by real space travel, the National Aeronautics and Space Administration (NASA) . Maybe that’s why the first MIPI Alliance® Developer’s Conference will be held in, Mountain View, California , near the NASA Ames Research Center . The real lesson to be learned is how the...

There is little doubt that Internet of Things has become the next big thing in business, in particular in semiconductor IP. The growing number of devices monitoring and adjusting our surroundings – lighting, temperature, sound volume and others has exploded in the recent years, and actually, so did the number of pins within an SoC that is needed to connect them all. Also, the use cases for the new generation of sensors...

The big buzz in the automotive industry lately is autonomous driving vehicles. Companies like Mercedes, BMW, Google, and Tesla have already released, or are soon to release, self-driving features that give the car some ability to drive itself. Several other companies are also currently working on this technology. As a result, future cars will be equipped with sensor clusters, more computing power, Car2X communication...

Flash memory is being utilized in computers and electronic devices found in Automotive, IoT, Drones, Connected Home, and other emerging applications, demanding ever higher transfer rates and lower latency. Expanding the flash Serial Peripheral Interface (SPI) accesses to 8 I/Os (hence Octal SPI) increases the Serial NOR Flash throughput and provide a more efficient solution for emerging applications, while providing...

If you design with flash memory components or IP solutions, head on over to the Santa Clara Convention Center to attend the Flash Memory Summit that is being held August 9-11 in Santa Clara, California. Cadence recently announced a partnership with Micron to support Micron’s high-performance, low pin count XTRMFlash interface as part of its controller IP portfolio. This new and faster NOR flash is going to revolutionize...

Growing deployment level of 10 Gigabit Ethernet in datacenters and automotive infotainment is driving the demand and the connectivity needs of a broad range of high-end, energy-efficient networking and computing applications. Energy-efficient networking in server area basically means elimination of packet loss, server virtualization with support for several applications and operating systems on a server; all by...

PCI-SIG Developers Conference 2016 is now history, taking place at the Santa Clara Convention Center at 28 th -29 th June, once again proving it’s not an event you want to miss. With PCIe 4.0 standard maturing, we’re seeing a lot of action in the market, though there are questions that have to be answered. There were questions about PCIe 5.0, and though it will become an important project, the SIG wisely is staying...

Cadence and ARM have created an IoT IP reference sub-system that can speed system development, enabling rapid prototyping and reducing time to market. The sub-system contains a processor and a set of peripherals that are typical for IoT sensors, giving a design team access to required functionality. Thus, the engineering effort is spent configuring the system, connecting the data stream to the cloud, and developing the...

Neural networks have become very popular today due to their use in leading-edge technology like deep learning machines, artificial intelligence, and virtual reality. Neural networks offer a powerful way to extract meaning in recognizing objects and actions within a visual stream. It's a topic with a lot of buzz today, and as the use of it becomes more and more pervasive, it’s just a matter of time before the devices...

PCI-SIG is a leading event in cloud infrastructure transformation, which is markets all over the world. We see a lot of market forces at work, creating urgency for PCIe Gen4 dynamics. Designers, system architects, engineers and engineering managers will be the driving force behind another PCI-SIG event. Taking place on June 28-29 2016 at the Santa Clara Convention Center, California, this prestigious event is filled...

For all IP providers, the ultimate proof of quality of their product is certification for standard compliance. Exhaustive testing conducted by third-party labs or at compliance workshops assess the behavior of the component across variety of conditions that can take place in customer’s application. Passing the compliance suite helps both convince existing prospects, as well as promote to get new ones. Cadence has...

Black-belt interface and memory protocol technologists will be at your disposal at this year’s DAC (Design Automation Conference) in Austin, Texas, June 5-9. You have to sign up for some activities, so please read carefully and don’t leave everything to the last minute. The Cadence Theater is located in our booth #107, and is a place to hear from our customers and partners about Cadence IP. You can see the entire Cadence...

The 21 st European Test Symposium (IEEE EST) took place in Amsterdam (Netherlands) from May 23 rd -27 th . With all the ideas and challenges in designing applications and with new trends in the area of electronic-based circuits and system testing, it was good to focus on some of the other important topics of achieving system success and a future-proofed design. And Cadence had the SerDes experience to share. The presentation...

With highly effective DDR4 and LPDDR4 class memories, it’s not always easy to know what kind of memory will best fit the needs of your application? What is the optimal compromise between keeping costs in check and optimizing performance? To answer that we have to take a step back and look at the history of the DDRs. In the PC memory area, we have the DDR2, DDR3 and DDR4. On the LPDDR front there are LPDDR2, LPDDR3...

Design&Reuse events are always exciting for their draw of an IP-centric audience. This year’s event was held in Bangalore, on April 6 th , and drew over 130 attendees. Experienced IP providers, fables IC vendors, external IP managers, internal reuse managers, foundries IP portfolio managers, IP market analysts, IP standard gurus. The scope of event is impressive, as represented by the breadth of presented concepts. ...

At Cadence we aim to enable our customers’ need to reduce their own design time and effort. That’s why we have worked closely with Hardent to develop a proven and integrated solution for MIPI Display Serial Interface and VESA Display Stream Compression IP. It provides visually lossless compression that reduces bandwidth by up to 3X. The demonstration of this solution first took place at CDNLive in Silicon Valley. It...

This year’s Open Server Summit served up plates full of data…if it wasn’t obvious, there’s more data coming. And then more for dessert. So much so that the challenges seem insurmountable to some. Others see huge opportunities, or a need, to disrupt the server market. Or to change the architecture of these systems to better handle new demands. According to Cisco Systems, annual datacenter traffic is expected to reach...

When a presentation makes us think about an industry on a whole new level and rethink potential outcomes for something significant in our lives, it’s a huge success. This year’s CDNLive San Jose was great for both Cadence and the industry, and here’s why. Overall, 75% presentations were from customers, and great keynotes (details below) engaged the other attendees. The keynotes on the future of the Internet of Things...

Anaheim Convention Center (CA) was the center of a spectacle of technology that continues to impact our daily lives, culminating decades of innovation in communications computer imaging. There were 580 exhibiting companies, accompanied by more than 1,160 peer-reviewed papers and more than 13,000 attendees. This years’ edition of Optical Fiber Conference (OFC), the largest optical communications and networking conference...

We have an exciting Design IP track at CDNLive Silicon Valley again this year. ARM, Mellanox, Broadcom, and Hardent talk about important IP technology topics. And Cadence will be sharing some of the latest about our technology development. Take a look at the full agenda —and don't miss the Design IP track (track 11) on Wednesday! The Design IP track is comprised of: DES201: Dinesh Venkatachalam, Broadcom...