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Welcome to my blog – I hope you find it useful, or at least entertaining.
My background is that I did chip design for 16 years before entering the EDA biz. I focused on front end design, doing RTL coding, testbench development, synthesis, and working with the place and route teams. As I moved along, I started leading teams, passing on my “wisdom”. I also started looking more and more at the architectures of these chips, trying to figure out how to make things efficient and fast.
This was pretty cool – doing high performance graphics. Along the way, I had some multi-million unit sellers, and some that, um, weren’t. A high point was winning a PC Magazine Editor’s Choice Award for one of the chips I worked on. The low point was being told by a major customer that we were too late – we had missed our market window by two weeks. Oh, and that was for the same chip. In the end, we were competing against nVidia and ATI, so you can guess why I entered EDA.
Actually though, if you guessed that it was because it wasn’t competing against nVidia and ATI, you’d only be partially right. Having slogged through multiple tapeouts, I figured there had to be a better way. There had to be something more than dealing with bugs, working around issues, manually verifying things, and the like. I had an intense interest in figuring out how to better use the technology I just *knew* was there. And I had an even more intense interest in “representing” designers in some of the internal discussions.
As you’ve probably figured out, I’ve been around for a bit. Or, as my daughter tells me, I’m old (no allowance for you, missy!). So let’s call this a blog for the “adults” out there. Now, I’m not trying to denigrate the other bloggers or readers. But I do think there’s a need for a blog for those of us who remember schematic capture (DN300 anyone?)
Ok – time for the question of the day. What would you like me to talk about? What would interest you? What kind of controversy should we stir up?
Finally, I want to give a plug for the GSA Suppliers Expo and Conference taking place next week in San Jose. I’ll be doing a panel session entitled, “Challenges in, and Solutions for, Design and Verification of Low Power Devices” moderated by Herb Reiter, President of eda 2 asic Consulting. The other panel members are Albert Chen, Field Application Marketing Manager from Faraday, and Don Kurelich, Technical Director, Sales Americas from Mentor Graphics. Check out this link. We’ve taken a vow not to use the words “UPF” or “CPF”, so it should be safe. I hope to see you there.
Again, welcome. And thanks for reading. If you have any feedback, I really want to hear it.