Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Being both old and an engineer, I’m cheap. I really like free stuff.
So, here are a few things you might find useful. And free.
Si2 has just recently approved Common Power Format (CPF) v1.1. This represents the third generation CPF standard, incorporating lessons and requirements learned over the past two years. Some significant enhancements include support for IP development and reuse (both hard and soft), secondary power domains, macro modeling, assertion control, improved mode transition control, pin/power domain association, and many more. The freebee here is the CPF v1.1 Pocket Reference. While I’m at it, I’ll throw in the CPF v1.1 spec.
Low Power design has a lot of nuances and subtleties. For example, how should assertions be handled in a power down domain when the power is cycled? What sort of formal verification strategy should be used to ensure that there are no power off cells on power control nets? How should test be structured so the die doesn’t burn up on the tester? And a lot more things like this. Fortunately, people have been down this road and have uncovered and solved some of these issues. The Power Forward team has collected a set of experiences into a guidebook – A Practical Guide to Low-Power Design. This includes chapters written by major LP players, including Freescale, NXP, ARM, ARC, and many others. There are also sections describing LP verification, design, implementation, and test – things to be careful of, and things to manage. And there are new chapters being added all the time. All you have to do is to give them your email address.
There have started to be some useful utilities started for power design. Maybe one reason why there aren’t more is the availability of a power intent parser. Well, Si2 has a CPF v1.0 parser available for free – just click here and you can get started. The stated purpose of this is to jumpstart the creation of products and tools. If anyone knows of a publicly available UPF parser (Accellera, IEEE, or other), let me know, and I’ll post that link here too.