Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I’ve shied away from getting into the power format wars – honestly, the whole question kind of bores me. I think everyone can agree that specifying your power intent in a single file that drives all the tools in the flow is a good thing. The specifics of which create_power_domain is used are less interesting.
But I think it is important to see how this whole thing was created, since it represents one of the more interesting developments in EDA in the past few years.
CPF began as an initiative in the RTL Compiler team in 2005. RC had introduced Low Power features the previous year, including isolation cell and level shifter cell insertion, and true top down Multi-Mode, Multi-Library synthesis. But the team was surprised that customers were slow to adopt this technology. They asked customers, and soon figured out that the main reason was because there was no real mechanism to validate that the power spec was correct. Since the isolation cells change the functionality, that new functionality needs to be tested. Without a way to ensure that the cells have the right values, there was just too much risk to the adoption.
Now, people had been working around this risk for a while, using home-grown PLI routines or even just force statements. But these techniques are limited and are costly to maintain. With the increased emphasis on LP design, a different, more structured technique was needed. And so the concept of a single power spec, driving every tool in the chain was born. This represented a significant investment for Cadence. In addition to developing a spec to drive a complete RTL to GDSII flow, all the tools in the flow would need to be updated and enhanced.
By the second quarter of 2006, a draft spec was ready and the initial tool implementations were available for deployment. Something like 300 person-years was spent to bring the prototype low power flow to customers. But the team realized that the flow needed industry test cases and validation. The spec needed to be proven, and needed experienced designer’s eyes on it. As a result, the Power Forward Initiative (PFI) was founded. The original ten members included AMD, ATI, ARM, NXP, Freescale, Fujitsu, NEC Electronics, Applied Materials, and TSMC. These are industry leaders who have a strong need for more automation in advanced low-power techniques. The PFI members agreed to review the spec and provide feedback that would refine the CPF specification and how it interacted with the tool chain. In addition, they agreed to do real projects, Proof Point Projects, to validate the requirements.
During the next 6 months, the PFI team provided over 500 separate inputs into the specification team. These new requirements and suggestions dramatically changed the spec, adding support for hierarchy, increased wildcards, tighter specification, and many other items. In addition, the first chip using CPF taped out around the end of 2006. This first tapeout proved the concepts and value of the single spec concept. There were real problems found in simulation, and real productivity enhancements.
By the end of 2006, the PFI team realized that the specification was production worthy and a standardization process was needed to take CPF to the next level of adoption. The decision was made to transfer the spec to Si2 for industry standardization. A Low Power Coalition (LPC) was set up inside Si2 to manage future updates to the spec. Si2 is now responsible for the specification with member companies having well –defined role in defining CPF’s evolution. At the same time, PFI membership grew – additional companies joined, including some EDA companies, additional design service companies, and more fabs. Currently, PFI membership stands at 36. PFI continues to do Proof Point Projects, proving new and advanced concepts in power specification for a range of design applications and low-power IP.
Si2 Low Power Coalition
Power Forward Initiative