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How many times has this happened to
you? The wireload model based timing engine in your synthesis tool indicates
that you have finally closed the timing on your design. You can now hand the
design off to the back end implementation engineer and focus on your other
tasks. A week or two go by and you get an email from the back end engineer
indicating that the timing is far from being met. He sends along an SDF
generated from the placed design. You drop what you are working on and take the
SDF into your synthesis tool to do additional optimization in order to again
close the timing. A week or so after sending the modified design to the back
end engineer you again get an email indicating that the timing looks better but
is not yet closed. Oh, there is also a new SDF attached to the email. Albert
Einstein once said "The definition of insanity is doing the same thing
over and over again and expecting different results." The root of this
insanity is that the proverbial wall between the front end design engineering
group and the back end implementation engineering group continues to be a
hindrance to rapid design closure. This is in part due to the long standing
inability of logical synthesis tools to accurately predict the design
characteristics after place and route. Techniques such as using SDF extracted
from a trial placement aren't viable since SDF only provides a static snapshot
of the placed design. Once any optimization is done the snapshot is
invalidated. The more optimization the less valid the snapshot becomes. The
current trend seems to be to push the timing closure task off to the back end.
However, this may not be the best place to do this sort of timing debugging
since the back end engineer doesn't have the intimate knowledge of the design
that is often required to close the timing. What if the only solution is an RTL
change? The fastest path to design closure would be for the front end engineer
to uncover the issues as opposed to waiting for the back end engineer to
uncover the issues late in the design cycle and then relating the discovery
back to the front end engineer so that a solution can be implemented. Not to
mention that your mental health would no doubt be grateful.
The key to rapid design closure is the
Silicon Virtual Prototype. An SVP takes the effects of placement and routing
into account and therefore is able to provide a reasonably accurate view of
physical design early in the implementation process. First Encounter is the SVP
tool of choice; however, First Encounter can be a daunting tool for a front end
engineer since a fair amount of implementation knowledge is required in order
to effectively use it. Also, the pressures of the project cycle do not allow
time to come up to speed on an entirely new tool. What the front end designer needs
is a way to reap the benefits of the SVP without having to understand the ins
and outs of the generation process. This is the motivation behind RTL Compiler
Physical. RC-Physical brings the First Encounter SVP into the front end domain
in a way that can easily be adopted by a front end engineer. For example, the
cockpit is the familiar synthesis environment which facilitates rapid
assimilation of the SVP methodology. The synthesis environment is RC,
therefore, the powerful global optimization techniques upon which RC is built
benefit from the improved accuracy of the interconnect modeling. Another
advantage of having the SVP integrated within the synthesis tool is that any
issues revealed by the SVP that can not be resolved with incremental
optimization can easily be linked back to the RTL in order to facilitate an
RC-Physical enables push button SVP
generation while also providing capability for the user to take more control of
the generation process if needed. Once the SVP is available to the front end
engineer, he is now able to leverage his vast knowledge of the design in order
to close the timing and address any other unforeseen issues that are revealed
now that the placement and routing estimation is present. Having the SVP
available within the synthesis tool makes this is a dynamic process. Once a
change has been made, all the repercussions of the change are immediately seen.
This means that the design can be closed through a process of efficient and
continual convergence. Once the design has been handed off to the back end
engineer, any timing problems that arise during the implementation process will
be addressed using gate based incremental optimization techniques. This means
that the back end engineer can achieve final design closure without having
intimate knowledge of the design itself. This leaves him free to focus on other
challenges associated with implementation.
The key to reducing the insanity
associated with design handoff is a matter of putting the right tools into the
right hands in order to facilitate rapid design closure.