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Each year, before I head off into vacation mode at the end of the year, I like to think back to what I learned through trends, to drive my 2009 personal goals and expectations.
In a nutshell, here's my view from visiting a large number of customers in North America, mostly in the San Jose area:
Chip Planning & Estimation: With the acquisition of ChipEstimate in March 2008, we improved our frontend offerings to begin with the design specification stage. No longer just an RTL-to-GDSII flow - now redefined and revolutionized as a Specification-to-GDSII flow (which is where customers begin their decision-making process). (I'll refer the standard flow to RTL-to-GDSII though in my future references, until Spec-to-GDSII is standardized, to keep things simple :) )
Synthesis: With added capabilities to the physical awareness flow, RTL Compiler has become even more well-positioned to deliver a quality RTL-to-GDSII flow with the SOCE backend. I have been waiting for years since the birth of physical synthesis for it to become a staple in everyone's flow. Maybe 2009 will be the year of general physical synthesis mass adoption driven by circumstance. Correlation continues to be key here, as well as improving quality of results.
Equivalency Checking: This remains a key critical highlight, as synthesis technologies continue to make significant improvements which can cause EC headaches. I look forward to the Conformal engineering team to continue to deliver even more exciting improvements using your feedback (click here for the a short survey) which will go directly to R&D (plus get entered to win a Wii and other exciting prize(s)!).
Low Power Design and Verification: In 2008, we saw a spike in the amount of low power design activity with our customers. Customers who used to have no need for looking at low power techniques are now doing it for reasons such as competition - "they do it, so we need to also" - as well as breaking the limits on their power requirements. Low power evangelist Steve Carlson wrote a nice short blurb on industry trends for low power designs on EETimes - co-hardware/software requirements as an emerging trend.
Engineering Change Orders (or more commonly infamously know as ECOs): 2008 marks the first anniversary of Verplex's (oops! :) ) - I mean Conformal's - ECO implementation tool. Customers tell us it's been hot for them (with tapeouts to prove it). I look forward to an even more exciting 2009 for C-ECO.
SDC Constraints Formal Verification: Golden design verification has been focused on for years. SDC timing constraints have not had this attention, and continue to be a pain (missed schedules, bad chips). In 2008, we saw a spike in customers that care about their SDCs and now want to do something about it using formal validation tools such as Conformal Constraint Designer. Perhaps 2009 will be the year for Golden SDC verification.
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As an AE for just over 2 years now, I am grateful to all my customers who have been supportive as well as challenged me to become a better customer advocate. Being a designer is one thing, being an AE is a whole different world!
To cap of the 2008 ...
To David Stokes, Jim Price: Thanks for enabling this great blogging opportunity!
To all my customers and readers: I hope you all had a wonderful Christmas vacation, and best wishes for 2009!