Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
These are follow up processors to their Shanghai core series. AMD has released both an energy efficient HE, and a high performance SE. These are AMD's entry into the quad core market, designed to compete directly with Intel's Xeon processor.
What I really found interesting was a mention of a new way of measuring power - Average CPU Power (ACP). The link to the white paper is: http://multicore.amd.com/resources/43761C_ACP_WP.pdf
Basically, ACP is measuring the power while running representative applications. The white paper specifically talks about the danger of looking only at peak power. From the story:
"It is of little value to measure power consumption by only looking at the spec sheets for different components, adding the totals together, because these generally only report the maximum power consumption. This scenario is like the car with a speedometer that tells you the maximum speed is 150MPH it's a maximum reading but it doesn't reflect daily usage."
This is the same problem many of my customers are also facing - how can they accurately determine the peak power of their chips while they can still impact the design? The old method of estimating switching activity just doesn't cut it. What I suspect really happens is that designers pad the estimate, leading to increased package and system cost.
"By utilizing ACP, customers can make a more educated estimate of their true power consumption. TDP, representing the thermal design power, is a rudimentary indicator of consumption, and may leave customers overestimating their data center infrastructure needs. In doing this, customers can potentially waste valuable data center space, resulting in un-optimized data centers that cost companies real dollars through their inefficiency."
AMD ran tests using a series of industry applications, and determined that the ACP reports are 23% to 34% less than the theoretical peak. So using this measurement can save a considerable amount of cost in building data centers.
Ok - that works for a server farm, but what about for a chip? How can you tell what is really running on a chip prior to tapeout, and how it affects power? Well, Cadence has had a solution for verifying actual operation for a long time - Palladium. And now we've enhanced it to perform Dynamic Power Analysis (DPA). This is up for EDN’s Innovation Award. The key thing is that this is not just counting activity - instead it is using RTL Compiler's power analysis capabilities to accurately capture the areas of peak power. Once identified, the design team can do something about it – maybe balance the load, maybe look at lowering the voltage. By having this knowledge before tapeout, the design team has been empowered to improve their chip's power profile (or ACP).
"AMD believes that ACP is a better way of thinking about typical CPU power that more accurately reflects the power consumption levels that customers can see in real life environments"
I couldn't agree more - measure the real power so you can take real actions.
ps: C-to-Silicon is also up for an EDN Innovation Award. I'll talk about ESL and power architecture selections in a future post.